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git01.mediatek.com / filogic / uboot / 6a51f189f1572ebd7bf1cf0c6b320a532be8eab1 / . / test / dm / panel.c
blob: 4d435a0d255c097f743f83e6298342693a707a68 [file] [log] [blame]
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Test for panel uclass
4 *
5 * Copyright (c) 2018 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
7 */
8
9#include <common.h>
10#include <backlight.h>
11#include <dm.h>
12#include <panel.h>
13#include <video.h>
14#include <asm/gpio.h>
15#include <asm/test.h>
16#include <dm/test.h>
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]17#include <power/regulator.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]18#include <test/test.h>
19#include <test/ut.h>
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]20
21/* Basic test of the panel uclass */
22static int dm_test_panel(struct unit_test_state *uts)
23{
24 struct udevice *dev, *pwm, *gpio, *reg;
25 uint period_ns;
26 uint duty_ns;
27 bool enable;
28 bool polarity;
29
30 ut_assertok(uclass_first_device_err(UCLASS_PANEL, &dev));
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300[diff] [blame]31 ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &pwm));
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]32 ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
33 ut_assertok(regulator_get_by_platname("VDD_EMMC_1.8V", &reg));
34 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
35 &enable, &polarity));
36 ut_asserteq(false, enable);
37 ut_asserteq(false, regulator_get_enable(reg));
38
39 ut_assertok(panel_enable_backlight(dev));
40 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
41 &enable, &polarity));
42 ut_asserteq(1000, period_ns);
Dario Binacchi753251d2020-10-11 14:28:04 +0200[diff] [blame]43 ut_asserteq(170 * 1000 / 255, duty_ns);
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]44 ut_asserteq(true, enable);
45 ut_asserteq(false, polarity);
46 ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
47 ut_asserteq(true, regulator_get_enable(reg));
48
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]49 ut_assertok(panel_set_backlight(dev, 40));
50 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
51 &enable, &polarity));
Dario Binacchi753251d2020-10-11 14:28:04 +0200[diff] [blame]52 ut_asserteq(64 * 1000 / 255, duty_ns);
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]53
54 ut_assertok(panel_set_backlight(dev, BACKLIGHT_MAX));
55 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
56 &enable, &polarity));
Dario Binacchi753251d2020-10-11 14:28:04 +0200[diff] [blame]57 ut_asserteq(255 * 1000 / 255, duty_ns);
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]58
59 ut_assertok(panel_set_backlight(dev, BACKLIGHT_MIN));
60 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
61 &enable, &polarity));
Dario Binacchi753251d2020-10-11 14:28:04 +0200[diff] [blame]62 ut_asserteq(0 * 1000 / 255, duty_ns);
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]63 ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
64
65 ut_assertok(panel_set_backlight(dev, BACKLIGHT_DEFAULT));
66 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
67 &enable, &polarity));
68 ut_asserteq(true, enable);
Dario Binacchi753251d2020-10-11 14:28:04 +0200[diff] [blame]69 ut_asserteq(170 * 1000 / 255, duty_ns);
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]70
71 ut_assertok(panel_set_backlight(dev, BACKLIGHT_OFF));
72 ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
73 &enable, &polarity));
Dario Binacchi753251d2020-10-11 14:28:04 +0200[diff] [blame]74 ut_asserteq(0 * 1000 / 255, duty_ns);
Simon Glassfe68a452018-10-01 12:22:41 -0600[diff] [blame]75 ut_asserteq(0, sandbox_gpio_get_value(gpio, 1));
76 ut_asserteq(false, regulator_get_enable(reg));
77
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]78 return 0;
79}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]80DM_TEST(dm_test_panel, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);