blob: 4cf977e20a30ea8dbfbda83f99645561b75c8909 [file] [log] [blame]
Adrian Alonso2b3d9612015-09-02 13:54:19 -05001/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/sys_proto.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020012#include <asm/mach-imx/boot_mode.h>
13#include <asm/mach-imx/dma.h>
14#include <asm/mach-imx/hab.h>
15#include <asm/mach-imx/rdc-sema.h>
Peng Fan47842492016-01-28 16:55:09 +080016#include <asm/arch/imx-rdc.h>
Adrian Alonso2b3d9612015-09-02 13:54:19 -050017#include <asm/arch/crm_regs.h>
18#include <dm.h>
19#include <imx_thermal.h>
20
Adrian Alonso2b3d9612015-09-02 13:54:19 -050021#if defined(CONFIG_IMX_THERMAL)
22static const struct imx_thermal_plat imx7_thermal_plat = {
23 .regs = (void *)ANATOP_BASE_ADDR,
24 .fuse_bank = 3,
25 .fuse_word = 3,
26};
27
28U_BOOT_DEVICE(imx7_thermal) = {
29 .name = "imx_thermal",
30 .platdata = &imx7_thermal_plat,
31};
32#endif
33
Peng Fan47842492016-01-28 16:55:09 +080034#ifdef CONFIG_IMX_RDC
35/*
36 * In current design, if any peripheral was assigned to both A7 and M4,
37 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
38 * low power mode. So M4 sleep will cause some peripherals fail to work
39 * at A7 core side. At default, all resources are in domain 0 - 3.
40 *
41 * There are 26 peripherals impacted by this IC issue:
42 * SIM2(sim2/emvsim2)
43 * SIM1(sim1/emvsim1)
44 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
45 * SAI1/SAI2/SAI3
46 * WDOG1/WDOG2/WDOG3/WDOG4
47 * GPT1/GPT2/GPT3/GPT4
48 * PWM1/PWM2/PWM3/PWM4
49 * ENET1/ENET2
50 * Software Workaround:
51 * Here we setup some resources to domain 0 where M4 codes will move
52 * the M4 out of this domain. Then M4 is not able to access them any longer.
53 * This is a workaround for ic issue. So the peripherals are not shared
54 * by them. This way requires the uboot implemented the RDC driver and
55 * set the 26 IPs above to domain 0 only. M4 code will assign resource
56 * to its own domain, if it want to use the resource.
57 */
58static rdc_peri_cfg_t const resources[] = {
59 (RDC_PER_SIM1 | RDC_DOMAIN(0)),
60 (RDC_PER_SIM2 | RDC_DOMAIN(0)),
61 (RDC_PER_UART1 | RDC_DOMAIN(0)),
62 (RDC_PER_UART2 | RDC_DOMAIN(0)),
63 (RDC_PER_UART3 | RDC_DOMAIN(0)),
64 (RDC_PER_UART4 | RDC_DOMAIN(0)),
65 (RDC_PER_UART5 | RDC_DOMAIN(0)),
66 (RDC_PER_UART6 | RDC_DOMAIN(0)),
67 (RDC_PER_UART7 | RDC_DOMAIN(0)),
68 (RDC_PER_SAI1 | RDC_DOMAIN(0)),
69 (RDC_PER_SAI2 | RDC_DOMAIN(0)),
70 (RDC_PER_SAI3 | RDC_DOMAIN(0)),
71 (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
72 (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
73 (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
74 (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
75 (RDC_PER_GPT1 | RDC_DOMAIN(0)),
76 (RDC_PER_GPT2 | RDC_DOMAIN(0)),
77 (RDC_PER_GPT3 | RDC_DOMAIN(0)),
78 (RDC_PER_GPT4 | RDC_DOMAIN(0)),
79 (RDC_PER_PWM1 | RDC_DOMAIN(0)),
80 (RDC_PER_PWM2 | RDC_DOMAIN(0)),
81 (RDC_PER_PWM3 | RDC_DOMAIN(0)),
82 (RDC_PER_PWM4 | RDC_DOMAIN(0)),
83 (RDC_PER_ENET1 | RDC_DOMAIN(0)),
84 (RDC_PER_ENET2 | RDC_DOMAIN(0)),
85};
86
87static void isolate_resource(void)
88{
89 imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
90}
91#endif
92
Adrian Alonsofcc8cb32015-10-12 13:48:13 -050093#if defined(CONFIG_SECURE_BOOT)
94struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
95 .bank = 1,
96 .word = 3,
97};
98#endif
99
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500100/*
101 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
102 * defines a 2-bit SPEED_GRADING
103 */
104#define OCOTP_TESTER3_SPEED_SHIFT 8
105#define OCOTP_TESTER3_SPEED_800MHZ 0
Fabio Estevam24fc0e62017-02-22 12:43:25 -0300106#define OCOTP_TESTER3_SPEED_500MHZ 1
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500107#define OCOTP_TESTER3_SPEED_1GHZ 2
Fabio Estevam3a797582017-02-22 12:43:27 -0300108#define OCOTP_TESTER3_SPEED_1P2GHZ 3
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500109
110u32 get_cpu_speed_grade_hz(void)
111{
112 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
113 struct fuse_bank *bank = &ocotp->bank[1];
114 struct fuse_bank1_regs *fuse =
115 (struct fuse_bank1_regs *)bank->fuse_regs;
116 uint32_t val;
117
118 val = readl(&fuse->tester3);
119 val >>= OCOTP_TESTER3_SPEED_SHIFT;
120 val &= 0x3;
121
122 switch(val) {
123 case OCOTP_TESTER3_SPEED_800MHZ:
Fabio Estevama296ef52017-02-22 12:43:26 -0300124 return 800000000;
Fabio Estevam24fc0e62017-02-22 12:43:25 -0300125 case OCOTP_TESTER3_SPEED_500MHZ:
126 return 500000000;
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500127 case OCOTP_TESTER3_SPEED_1GHZ:
Fabio Estevama296ef52017-02-22 12:43:26 -0300128 return 1000000000;
Fabio Estevam3a797582017-02-22 12:43:27 -0300129 case OCOTP_TESTER3_SPEED_1P2GHZ:
130 return 1200000000;
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500131 }
132 return 0;
133}
134
135/*
136 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
137 * defines a 2-bit SPEED_GRADING
138 */
139#define OCOTP_TESTER3_TEMP_SHIFT 6
140
141u32 get_cpu_temp_grade(int *minc, int *maxc)
142{
143 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
144 struct fuse_bank *bank = &ocotp->bank[1];
145 struct fuse_bank1_regs *fuse =
146 (struct fuse_bank1_regs *)bank->fuse_regs;
147 uint32_t val;
148
149 val = readl(&fuse->tester3);
150 val >>= OCOTP_TESTER3_TEMP_SHIFT;
151 val &= 0x3;
152
153 if (minc && maxc) {
Peng Fan6669fff2015-09-15 14:05:08 +0800154 if (val == TEMP_AUTOMOTIVE) {
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500155 *minc = -40;
156 *maxc = 125;
157 } else if (val == TEMP_INDUSTRIAL) {
158 *minc = -40;
159 *maxc = 105;
160 } else if (val == TEMP_EXTCOMMERCIAL) {
161 *minc = -20;
162 *maxc = 105;
163 } else {
164 *minc = 0;
165 *maxc = 95;
166 }
167 }
168 return val;
169}
170
Fabio Estevamf6ced1b2016-02-28 12:33:17 -0300171static bool is_mx7d(void)
172{
173 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
174 struct fuse_bank *bank = &ocotp->bank[1];
175 struct fuse_bank1_regs *fuse =
176 (struct fuse_bank1_regs *)bank->fuse_regs;
177 int val;
178
179 val = readl(&fuse->tester4);
180 if (val & 1)
181 return false;
182 else
183 return true;
184}
185
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500186u32 get_cpu_rev(void)
187{
188 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
189 ANATOP_BASE_ADDR;
190 u32 reg = readl(&ccm_anatop->digprog);
191 u32 type = (reg >> 16) & 0xff;
192
Fabio Estevamf6ced1b2016-02-28 12:33:17 -0300193 if (!is_mx7d())
194 type = MXC_CPU_MX7S;
195
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500196 reg &= 0xff;
197 return (type << 12) | reg;
198}
199
200#ifdef CONFIG_REVISION_TAG
201u32 __weak get_board_rev(void)
202{
203 return get_cpu_rev();
204}
205#endif
206
Peng Fanfcd53ce2015-10-23 10:13:04 +0800207/* enable all periherial can be accessed in nosec mode */
208static void init_csu(void)
209{
210 int i = 0;
211 for (i = 0; i < CSU_NUM_REGS; i++)
212 writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
213}
214
Peng Faneb518d52016-01-04 13:16:41 +0800215static void imx_enet_mdio_fixup(void)
216{
217 struct iomuxc_gpr_base_regs *gpr_regs =
218 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
219
220 /*
221 * The management data input/output (MDIO) requires open-drain,
222 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
223 * this feature. So to TO1.1, need to enable open drain by setting
224 * bits GPR0[8:7].
225 */
226
227 if (soc_rev() >= CHIP_REV_1_1) {
228 setbits_le32(&gpr_regs->gpr[0],
229 IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
230 }
231}
232
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500233int arch_cpu_init(void)
234{
235 init_aips();
236
Peng Fanfcd53ce2015-10-23 10:13:04 +0800237 init_csu();
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500238 /* Disable PDE bit of WMCR register */
239 imx_set_wdog_powerdown(false);
240
Peng Faneb518d52016-01-04 13:16:41 +0800241 imx_enet_mdio_fixup();
242
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500243#ifdef CONFIG_APBH_DMA
244 /* Start APBH DMA */
245 mxs_dma_init();
246#endif
247
Peng Fan47842492016-01-28 16:55:09 +0800248 if (IS_ENABLED(CONFIG_IMX_RDC))
249 isolate_resource();
250
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500251 return 0;
252}
253
Stefan Agner42dac202016-07-13 00:25:39 -0700254#ifdef CONFIG_ARCH_MISC_INIT
255int arch_misc_init(void)
256{
257#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
258 if (is_mx7d())
259 setenv("soc", "imx7d");
260 else
261 setenv("soc", "imx7s");
262#endif
263
264 return 0;
265}
266#endif
267
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500268#ifdef CONFIG_SERIAL_TAG
269void get_board_serial(struct tag_serialnr *serialnr)
270{
271 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
272 struct fuse_bank *bank = &ocotp->bank[0];
273 struct fuse_bank0_regs *fuse =
274 (struct fuse_bank0_regs *)bank->fuse_regs;
275
276 serialnr->low = fuse->tester0;
277 serialnr->high = fuse->tester1;
278}
279#endif
280
281#if defined(CONFIG_FEC_MXC)
282void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
283{
284 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
285 struct fuse_bank *bank = &ocotp->bank[9];
286 struct fuse_bank9_regs *fuse =
287 (struct fuse_bank9_regs *)bank->fuse_regs;
288
289 if (0 == dev_id) {
290 u32 value = readl(&fuse->mac_addr1);
291 mac[0] = (value >> 8);
292 mac[1] = value;
293
294 value = readl(&fuse->mac_addr0);
295 mac[2] = value >> 24;
296 mac[3] = value >> 16;
297 mac[4] = value >> 8;
298 mac[5] = value;
299 } else {
300 u32 value = readl(&fuse->mac_addr2);
301 mac[0] = value >> 24;
302 mac[1] = value >> 16;
303 mac[2] = value >> 8;
304 mac[3] = value;
305
306 value = readl(&fuse->mac_addr1);
307 mac[4] = value >> 24;
308 mac[5] = value >> 16;
309 }
310}
311#endif
312
Peng Fancf1367a2016-01-28 16:55:07 +0800313#ifdef CONFIG_IMX_BOOTAUX
314int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
315{
316 u32 stack, pc;
317 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
318
319 if (!boot_private_data)
320 return 1;
321
322 stack = *(u32 *)boot_private_data;
323 pc = *(u32 *)(boot_private_data + 4);
324
325 /* Set the stack and pc to M4 bootROM */
326 writel(stack, M4_BOOTROM_BASE_ADDR);
327 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
328
329 /* Enable M4 */
330 clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
331 SRC_M4RCR_ENABLE_M4_MASK);
332
333 return 0;
334}
335
336int arch_auxiliary_core_check_up(u32 core_id)
337{
338 uint32_t val;
339 struct src *src_reg = (struct src *)SRC_BASE_ADDR;
340
341 val = readl(&src_reg->m4rcr);
342 if (val & 0x00000001)
343 return 0; /* assert in reset */
344
345 return 1;
346}
347#endif
348
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500349void set_wdog_reset(struct wdog_regs *wdog)
350{
351 u32 reg = readw(&wdog->wcr);
352 /*
353 * Output WDOG_B signal to reset external pmic or POR_B decided by
354 * the board desgin. Without external reset, the peripherals/DDR/
355 * PMIC are not reset, that may cause system working abnormal.
356 */
357 reg = readw(&wdog->wcr);
358 reg |= 1 << 3;
359 /*
360 * WDZST bit is write-once only bit. Align this bit in kernel,
361 * otherwise kernel code will have no chance to set this bit.
362 */
363 reg |= 1 << 0;
364 writew(reg, &wdog->wcr);
365}
366
367/*
368 * cfg_val will be used for
369 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
370 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
371 * to SBMR1, which will determine the boot device.
372 */
373const struct boot_mode soc_boot_modes[] = {
374 {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
375 {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
376 {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
377 {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
378
379 {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
380 {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
381 /* 4 bit bus width */
382 {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
383 {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
384 {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
385 {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
386 {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
387 {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
388 {NULL, 0},
389};
390
391enum boot_device get_boot_device(void)
392{
393 struct bootrom_sw_info **p =
394 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
395
396 enum boot_device boot_dev = SD1_BOOT;
397 u8 boot_type = (*p)->boot_dev_type;
398 u8 boot_instance = (*p)->boot_dev_instance;
399
400 switch (boot_type) {
401 case BOOT_TYPE_SD:
402 boot_dev = boot_instance + SD1_BOOT;
403 break;
404 case BOOT_TYPE_MMC:
405 boot_dev = boot_instance + MMC1_BOOT;
406 break;
407 case BOOT_TYPE_NAND:
408 boot_dev = NAND_BOOT;
409 break;
410 case BOOT_TYPE_QSPI:
411 boot_dev = QSPI_BOOT;
412 break;
413 case BOOT_TYPE_WEIM:
414 boot_dev = WEIM_NOR_BOOT;
415 break;
416 case BOOT_TYPE_SPINOR:
417 boot_dev = SPI_NOR_BOOT;
418 break;
419 default:
420 break;
421 }
422
423 return boot_dev;
424}
425
Peng Fan6c9d8fb2016-01-28 16:51:25 +0800426#ifdef CONFIG_ENV_IS_IN_MMC
427__weak int board_mmc_get_env_dev(int devno)
428{
429 return CONFIG_SYS_MMC_ENV_DEV;
430}
431
432int mmc_get_env_dev(void)
433{
434 struct bootrom_sw_info **p =
435 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
436 int devno = (*p)->boot_dev_instance;
437 u8 boot_type = (*p)->boot_dev_type;
438
439 /* If not boot from sd/mmc, use default value */
440 if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
441 return CONFIG_SYS_MMC_ENV_DEV;
442
443 return board_mmc_get_env_dev(devno);
444}
445#endif
446
Adrian Alonso2b3d9612015-09-02 13:54:19 -0500447void s_init(void)
448{
449#if !defined CONFIG_SPL_BUILD
450 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
451 asm volatile(
452 "mrc p15, 0, r0, c1, c0, 1\n"
453 "orr r0, r0, #1 << 6\n"
454 "mcr p15, 0, r0, c1, c0, 1\n");
455#endif
456 /* clock configuration. */
457 clock_init();
458
459 return;
460}
Peng Fan99c874b2016-05-19 13:02:16 +0800461
462void reset_misc(void)
463{
464#ifdef CONFIG_VIDEO_MXS
465 lcdif_power_down();
466#endif
467}
468