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git01.mediatek.com / filogic / uboot / 6e2af916e852c735f094042119d80dba6b1fbe38 / . / arch / arm / include / asm / arch-mx7ulp / pcc.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fan684ccd92017-02-22 16:21:42 +0800[diff] [blame]4 */
5
6#ifndef _ASM_ARCH_PCC_H
7#define _ASM_ARCH_PCC_H
8
9#include <common.h>
10#include <asm/arch/scg.h>
11
12/* PCC2 */
13
14enum pcc2_entry {
15 /* On-Platform (32 entries) */
16 RSVD0_PCC2_SLOT = 0,
17 RSVD1_PCC2_SLOT = 1,
18 CA7_GIC_PCC2_SLOT = 2,
19 RSVD3_PCC2_SLOT = 3,
20 RSVD4_PCC2_SLOT = 4,
21 RSVD5_PCC2_SLOT = 5,
22 RSVD6_PCC2_SLOT = 6,
23 RSVD7_PCC2_SLOT = 7,
24 DMA1_PCC2_SLOT = 8,
25 RSVD9_PCC2_SLOT = 9,
26 RSVD10_PCC2_SLOT = 10,
27 RSVD11_PCC2_SLOT = 11,
28 RSVD12_PCC2_SLOT = 12,
29 RSVD13_PCC2_SLOT = 13,
30 RSVD14_PCC2_SLOT = 14,
31 RGPIO1_PCC2_SLOT = 15,
32 FLEXBUS0_PCC2_SLOT = 16,
33 RSVD17_PCC2_SLOT = 17,
34 RSVD18_PCC2_SLOT = 18,
35 RSVD19_PCC2_SLOT = 19,
36 RSVD20_PCC2_SLOT = 20,
37 RSVD21_PCC2_SLOT = 21,
38 RSVD22_PCC2_SLOT = 22,
39 RSVD23_PCC2_SLOT = 23,
40 RSVD24_PCC2_SLOT = 24,
41 RSVD25_PCC2_SLOT = 25,
42 RSVD26_PCC2_SLOT = 26,
43 SEMA42_1_PCC2_SLOT = 27,
44 RSVD28_PCC2_SLOT = 28,
45 RSVD29_PCC2_SLOT = 29,
46 RSVD30_PCC2_SLOT = 30,
47 RSVD31_PCC2_SLOT = 31,
48
49 /* Off-Platform (96 entries) */
50 RSVD32_PCC2_SLOT = 32,
51 DMA1_CH_MUX0_PCC2_SLOT = 33,
52 MU_B_PCC2_SLOT = 34,
53 SNVS_PCC2_SLOT = 35,
54 CAAM_PCC2_SLOT = 36,
55 LPTPM4_PCC2_SLOT = 37,
56 LPTPM5_PCC2_SLOT = 38,
57 LPIT1_PCC2_SLOT = 39,
58 RSVD40_PCC2_SLOT = 40,
59 LPSPI2_PCC2_SLOT = 41,
60 LPSPI3_PCC2_SLOT = 42,
61 LPI2C4_PCC2_SLOT = 43,
62 LPI2C5_PCC2_SLOT = 44,
63 LPUART4_PCC2_SLOT = 45,
64 LPUART5_PCC2_SLOT = 46,
65 RSVD47_PCC2_SLOT = 47,
66 RSVD48_PCC2_SLOT = 48,
67 FLEXIO1_PCC2_SLOT = 49,
68 RSVD50_PCC2_SLOT = 50,
69 USBOTG0_PCC2_SLOT = 51,
70 USBOTG1_PCC2_SLOT = 52,
71 USBPHY_PCC2_SLOT = 53,
72 USB_PL301_PCC2_SLOT = 54,
73 USDHC0_PCC2_SLOT = 55,
74 USDHC1_PCC2_SLOT = 56,
75 RSVD57_PCC2_SLOT = 57,
76 TRGMUX1_PCC2_SLOT = 58,
77 RSVD59_PCC2_SLOT = 59,
78 RSVD60_PCC2_SLOT = 60,
79 WDG1_PCC2_SLOT = 61,
80 SCG1_PCC2_SLOT = 62,
81 PCC2_PCC2_SLOT = 63,
82 PMC1_PCC2_SLOT = 64,
83 SMC1_PCC2_SLOT = 65,
84 RCM1_PCC2_SLOT = 66,
85 WDG2_PCC2_SLOT = 67,
86 RSVD68_PCC2_SLOT = 68,
87 TEST_SPACE1_PCC2_SLOT = 69,
88 TEST_SPACE2_PCC2_SLOT = 70,
89 TEST_SPACE3_PCC2_SLOT = 71,
90 RSVD72_PCC2_SLOT = 72,
91 RSVD73_PCC2_SLOT = 73,
92 RSVD74_PCC2_SLOT = 74,
93 RSVD75_PCC2_SLOT = 75,
94 RSVD76_PCC2_SLOT = 76,
95 RSVD77_PCC2_SLOT = 77,
96 RSVD78_PCC2_SLOT = 78,
97 RSVD79_PCC2_SLOT = 79,
98 RSVD80_PCC2_SLOT = 80,
99 RSVD81_PCC2_SLOT = 81,
100 RSVD82_PCC2_SLOT = 82,
101 RSVD83_PCC2_SLOT = 83,
102 RSVD84_PCC2_SLOT = 84,
103 RSVD85_PCC2_SLOT = 85,
104 RSVD86_PCC2_SLOT = 86,
105 RSVD87_PCC2_SLOT = 87,
106 RSVD88_PCC2_SLOT = 88,
107 RSVD89_PCC2_SLOT = 89,
108 RSVD90_PCC2_SLOT = 90,
109 RSVD91_PCC2_SLOT = 91,
110 RSVD92_PCC2_SLOT = 92,
111 RSVD93_PCC2_SLOT = 93,
112 RSVD94_PCC2_SLOT = 94,
113 RSVD95_PCC2_SLOT = 95,
114 RSVD96_PCC2_SLOT = 96,
115 RSVD97_PCC2_SLOT = 97,
116 RSVD98_PCC2_SLOT = 98,
117 RSVD99_PCC2_SLOT = 99,
118 RSVD100_PCC2_SLOT = 100,
119 RSVD101_PCC2_SLOT = 101,
120 RSVD102_PCC2_SLOT = 102,
121 RSVD103_PCC2_SLOT = 103,
122 RSVD104_PCC2_SLOT = 104,
123 RSVD105_PCC2_SLOT = 105,
124 RSVD106_PCC2_SLOT = 106,
125 RSVD107_PCC2_SLOT = 107,
126 RSVD108_PCC2_SLOT = 108,
127 RSVD109_PCC2_SLOT = 109,
128 RSVD110_PCC2_SLOT = 110,
129 RSVD111_PCC2_SLOT = 111,
130 RSVD112_PCC2_SLOT = 112,
131 RSVD113_PCC2_SLOT = 113,
132 RSVD114_PCC2_SLOT = 114,
133 RSVD115_PCC2_SLOT = 115,
134 RSVD116_PCC2_SLOT = 116,
135 RSVD117_PCC2_SLOT = 117,
136 RSVD118_PCC2_SLOT = 118,
137 RSVD119_PCC2_SLOT = 119,
138 RSVD120_PCC2_SLOT = 120,
139 RSVD121_PCC2_SLOT = 121,
140 RSVD122_PCC2_SLOT = 122,
141 RSVD123_PCC2_SLOT = 123,
142 RSVD124_PCC2_SLOT = 124,
143 RSVD125_PCC2_SLOT = 125,
144 RSVD126_PCC2_SLOT = 126,
145 RSVD127_PCC2_SLOT = 127,
146};
147
148enum pcc3_entry {
149 /* On-Platform (32 entries) */
150 RSVD0_PCC3_SLOT = 0,
151 RSVD1_PCC3_SLOT = 1,
152 RSVD2_PCC3_SLOT = 2,
153 RSVD3_PCC3_SLOT = 3,
154 RSVD4_PCC3_SLOT = 4,
155 RSVD5_PCC3_SLOT = 5,
156 RSVD6_PCC3_SLOT = 6,
157 RSVD7_PCC3_SLOT = 7,
158 RSVD8_PCC3_SLOT = 8,
159 RSVD9_PCC3_SLOT = 9,
160 RSVD10_PCC3_SLOT = 10,
161 RSVD11_PCC3_SLOT = 11,
162 RSVD12_PCC3_SLOT = 12,
163 RSVD13_PCC3_SLOT = 13,
164 RSVD14_PCC3_SLOT = 14,
165 RSVD15_PCC3_SLOT = 15,
166 ROMCP1_PCC3_SLOT = 16,
167 RSVD17_PCC3_SLOT = 17,
168 RSVD18_PCC3_SLOT = 18,
169 RSVD19_PCC3_SLOT = 19,
170 RSVD20_PCC3_SLOT = 20,
171 RSVD21_PCC3_SLOT = 21,
172 RSVD22_PCC3_SLOT = 22,
173 RSVD23_PCC3_SLOT = 23,
174 RSVD24_PCC3_SLOT = 24,
175 RSVD25_PCC3_SLOT = 25,
176 RSVD26_PCC3_SLOT = 26,
177 RSVD27_PCC3_SLOT = 27,
178 RSVD28_PCC3_SLOT = 28,
179 RSVD29_PCC3_SLOT = 29,
180 RSVD30_PCC3_SLOT = 30,
181 RSVD31_PCC3_SLOT = 31,
182
183 /* Off-Platform (96 entries) */
184 RSVD32_PCC3_SLOT = 32,
185 LPTPM6_PCC3_SLOT = 33,
186 LPTPM7_PCC3_SLOT = 34,
187 RSVD35_PCC3_SLOT = 35,
188 LPI2C6_PCC3_SLOT = 36,
189 LPI2C7_PCC3_SLOT = 37,
190 LPUART6_PCC3_SLOT = 38,
191 LPUART7_PCC3_SLOT = 39,
192 VIU0_PCC3_SLOT = 40,
193 DSI0_PCC3_SLOT = 41,
194 LCDIF0_PCC3_SLOT = 42,
195 MMDC0_PCC3_SLOT = 43,
196 IOMUXC1_PCC3_SLOT = 44,
197 IOMUXC_DDR_PCC3_SLOT = 45,
198 PORTC_PCC3_SLOT = 46,
199 PORTD_PCC3_SLOT = 47,
200 PORTE_PCC3_SLOT = 48,
201 PORTF_PCC3_SLOT = 49,
202 RSVD50_PCC3_SLOT = 50,
203 PCC3_PCC3_SLOT = 51,
204 RSVD52_PCC3_SLOT = 52,
205 WKPU_PCC3_SLOT = 53,
206 RSVD54_PCC3_SLOT = 54,
207 RSVD55_PCC3_SLOT = 55,
208 RSVD56_PCC3_SLOT = 56,
209 RSVD57_PCC3_SLOT = 57,
210 RSVD58_PCC3_SLOT = 58,
211 RSVD59_PCC3_SLOT = 59,
212 RSVD60_PCC3_SLOT = 60,
213 RSVD61_PCC3_SLOT = 61,
214 RSVD62_PCC3_SLOT = 62,
215 RSVD63_PCC3_SLOT = 63,
216 RSVD64_PCC3_SLOT = 64,
217 RSVD65_PCC3_SLOT = 65,
218 RSVD66_PCC3_SLOT = 66,
219 RSVD67_PCC3_SLOT = 67,
220 RSVD68_PCC3_SLOT = 68,
221 RSVD69_PCC3_SLOT = 69,
222 RSVD70_PCC3_SLOT = 70,
223 RSVD71_PCC3_SLOT = 71,
224 RSVD72_PCC3_SLOT = 72,
225 RSVD73_PCC3_SLOT = 73,
226 RSVD74_PCC3_SLOT = 74,
227 RSVD75_PCC3_SLOT = 75,
228 RSVD76_PCC3_SLOT = 76,
229 RSVD77_PCC3_SLOT = 77,
230 RSVD78_PCC3_SLOT = 78,
231 RSVD79_PCC3_SLOT = 79,
232 RSVD80_PCC3_SLOT = 80,
233 GPU3D_PCC3_SLOT = 81,
234 GPU2D_PCC3_SLOT = 82,
235 RSVD83_PCC3_SLOT = 83,
236 RSVD84_PCC3_SLOT = 84,
237 RSVD85_PCC3_SLOT = 85,
238 RSVD86_PCC3_SLOT = 86,
239 RSVD87_PCC3_SLOT = 87,
240 RSVD88_PCC3_SLOT = 88,
241 RSVD89_PCC3_SLOT = 89,
242 RSVD90_PCC3_SLOT = 90,
243 RSVD91_PCC3_SLOT = 91,
244 RSVD92_PCC3_SLOT = 92,
245 RSVD93_PCC3_SLOT = 93,
246 RSVD94_PCC3_SLOT = 94,
247 RSVD95_PCC3_SLOT = 95,
248 RSVD96_PCC3_SLOT = 96,
249 RSVD97_PCC3_SLOT = 97,
250 RSVD98_PCC3_SLOT = 98,
251 RSVD99_PCC3_SLOT = 99,
252 RSVD100_PCC3_SLOT = 100,
253 RSVD101_PCC3_SLOT = 101,
254 RSVD102_PCC3_SLOT = 102,
255 RSVD103_PCC3_SLOT = 103,
256 RSVD104_PCC3_SLOT = 104,
257 RSVD105_PCC3_SLOT = 105,
258 RSVD106_PCC3_SLOT = 106,
259 RSVD107_PCC3_SLOT = 107,
260 RSVD108_PCC3_SLOT = 108,
261 RSVD109_PCC3_SLOT = 109,
262 RSVD110_PCC3_SLOT = 110,
263 RSVD111_PCC3_SLOT = 111,
264 RSVD112_PCC3_SLOT = 112,
265 RSVD113_PCC3_SLOT = 113,
266 RSVD114_PCC3_SLOT = 114,
267 RSVD115_PCC3_SLOT = 115,
268 RSVD116_PCC3_SLOT = 116,
269 RSVD117_PCC3_SLOT = 117,
270 RSVD118_PCC3_SLOT = 118,
271 RSVD119_PCC3_SLOT = 119,
272 RSVD120_PCC3_SLOT = 120,
273 RSVD121_PCC3_SLOT = 121,
274 RSVD122_PCC3_SLOT = 122,
275 RSVD123_PCC3_SLOT = 123,
276 RSVD124_PCC3_SLOT = 124,
277 RSVD125_PCC3_SLOT = 125,
278 RSVD126_PCC3_SLOT = 126,
279 RSVD127_PCC3_SLOT = 127,
280};
281
282
283/* PCC registers */
284#define PCC_PR_OFFSET 31
285#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
286#define PCC_CGC_OFFSET 30
287#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
288#define PCC_INUSE_OFFSET 29
289#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
290#define PCC_PCS_OFFSET 24
291#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
292#define PCC_FRAC_OFFSET 4
293#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
294#define PCC_PCD_OFFSET 0
295#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET)
296
297
298enum pcc_clksrc_type {
299 CLKSRC_PER_PLAT = 0,
300 CLKSRC_PER_BUS = 1,
301 CLKSRC_NO_PCS = 2,
302};
303
304enum pcc_div_type {
305 PCC_HAS_DIV,
306 PCC_NO_DIV,
307};
308
309/* All peripheral clocks on A7 PCCs */
310enum pcc_clk {
311 /*PCC2 clocks*/
312 PER_CLK_DMA1 = 0,
313 PER_CLK_RGPIO2P1,
314 PER_CLK_FLEXBUS,
315 PER_CLK_SEMA42_1,
316 PER_CLK_DMA_MUX1,
317 PER_CLK_SNVS,
318 PER_CLK_CAAM,
319 PER_CLK_LPTPM4,
320 PER_CLK_LPTPM5,
321 PER_CLK_LPIT1,
322 PER_CLK_LPSPI2,
323 PER_CLK_LPSPI3,
324 PER_CLK_LPI2C4,
325 PER_CLK_LPI2C5,
326 PER_CLK_LPUART4,
327 PER_CLK_LPUART5,
328 PER_CLK_FLEXIO1,
329 PER_CLK_USB0,
330 PER_CLK_USB1,
331 PER_CLK_USB_PHY,
332 PER_CLK_USB_PL301,
333 PER_CLK_USDHC0,
334 PER_CLK_USDHC1,
335 PER_CLK_WDG1,
336 PER_CLK_WDG2,
337
338 /*PCC3 clocks*/
339 PER_CLK_LPTPM6,
340 PER_CLK_LPTPM7,
341 PER_CLK_LPI2C6,
342 PER_CLK_LPI2C7,
343 PER_CLK_LPUART6,
344 PER_CLK_LPUART7,
345 PER_CLK_VIU,
346 PER_CLK_DSI,
347 PER_CLK_LCDIF,
348 PER_CLK_MMDC,
349 PER_CLK_PCTLC,
350 PER_CLK_PCTLD,
351 PER_CLK_PCTLE,
352 PER_CLK_PCTLF,
353 PER_CLK_GPU3D,
354 PER_CLK_GPU2D,
355};
356
357
358/* This structure keeps info for each pcc slot */
359struct pcc_entry {
360 u32 pcc_base;
361 u32 pcc_slot;
362 enum pcc_clksrc_type clksrc;
363 enum pcc_div_type div;
364};
365
366int pcc_clock_enable(enum pcc_clk clk, bool enable);
367int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
368int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
369bool pcc_clock_is_enable(enum pcc_clk clk);
370int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
371u32 pcc_clock_get_rate(enum pcc_clk clk);
372#endif