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git01.mediatek.com / filogic / uboot / 69c925f20e82b04ee18240c471d83efb2563b050 / . / include / asm-arm / arch-at91sam9 / at91sam9263_matrix.h
blob: 83aaaab77319726e0a8f8e859021c32a08a4efa1 [file] [log] [blame]
Stelian Pop69c925f2008-05-08 18:52:23 +0200[diff] [blame^]1/*
2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h]
3 *
4 * Copyright (C) 2006 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9263 datasheet revision B (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
30#define AT91_MATRIX_ULBT_FOUR (2 << 0)
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33
34#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51
52#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
71#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
72#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
73#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
74#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77
78#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2)
82#define AT91_MATRIX_RCB3 (1 << 3)
83#define AT91_MATRIX_RCB4 (1 << 4)
84#define AT91_MATRIX_RCB5 (1 << 5)
85#define AT91_MATRIX_RCB6 (1 << 6)
86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8)
88
89#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0)
93#define AT91_MATRIX_ITCM_32 (6 << 0)
94#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
95#define AT91_MATRIX_DTCM_0 (0 << 4)
96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4)
98
99#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
103#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
104#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
105#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
106#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
107#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
108#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
109#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
110#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
111#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
112#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
113#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116
117#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
121#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
122#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
123#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
124#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
125#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
126#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
127#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
128
129#endif