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git01.mediatek.com / filogic / uboot / 692f872e7a9f4d6168a18fa22cc72de88e6c3926 / . / arch / arm / dts / k3-j721s2-common-proc-board-u-boot.dtsi
blob: a3ebf5996eacc52c64451e6be9dd30dd4b9f145a [file] [log] [blame]
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]3 * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]4 */
5
Neha Malcom Francis9409fb62023-07-22 00:14:36 +0530[diff] [blame]6#include "k3-j721s2-binman.dtsi"
7
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]8&wkup_i2c0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]9 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]10};
11
12&cbass_main {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]13 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]14};
15
16&main_navss {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]17 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]18};
19
20&cbass_mcu_wakeup {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]21 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]22
23 chipid@43000014 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]24 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]25 };
26};
27
28&mcu_navss {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]29 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]30};
31
32&mcu_ringacc {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]33 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]34};
35
36&mcu_udmap {
37 reg = <0x0 0x285c0000 0x0 0x100>,
38 <0x0 0x284c0000 0x0 0x4000>,
39 <0x0 0x2a800000 0x0 0x40000>,
40 <0x0 0x284a0000 0x0 0x4000>,
41 <0x0 0x2aa00000 0x0 0x40000>,
42 <0x0 0x28400000 0x0 0x2000>;
43 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
44 "tchanrt", "rflow";
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]45 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]46};
47
48&secure_proxy_main {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]49 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]50};
51
52&sms {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]53 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]54 k3_sysreset: sysreset-controller {
55 compatible = "ti,sci-sysreset";
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]56 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]57 };
58};
59
60&main_pmx0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]61 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]62};
63
64&main_uart8_pins_default {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]65 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]66};
67
68&main_mmc1_pins_default {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]69 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]70};
71
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]72&main_usbss0_pins_default {
73 bootph-all;
74};
75
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]76&wkup_pmx0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]77 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]78};
79
80&k3_pds {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]81 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]82};
83
84&k3_clks {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]85 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]86};
87
88&k3_reset {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]89 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]90};
91
92&main_uart8 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]93 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]94};
95
96&mcu_uart0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]97 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]98};
99
100&wkup_uart0 {
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]101 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]102};
103
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]104&main_sdhci0 {
105 bootph-all;
106};
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]107
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]108&main_sdhci1 {
109 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]110};
111
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]112&ospi0 {
113 status = "disabled";
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]114};
115
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530[diff] [blame]116&ospi1 {
117 status = "disabled";
118};
119
120&usbss0 {
121 bootph-all;
122};
123
124&usb0 {
125 dr_mode = "peripheral";
126 bootph-all;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]127};