Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 692f872e7a9f4d6168a18fa22cc72de88e6c3926 / . / arch / arm / dts / imx8mp-beacon-kit-u-boot.dtsi
blob: 393fd8ec2e5bd9672b7103020980a7b3e8a1f399 [file] [log] [blame]
Adam Forda8554812023-03-23 22:06:16 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
12 bootph-pre-ram;
13 };
Adam Forda8554812023-03-23 22:06:16 -0500[diff] [blame]14};
15
16&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
17 bootph-pre-ram;
18};
19
20&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
21 bootph-pre-ram;
22};
23
Adam Forda8554812023-03-23 22:06:16 -0500[diff] [blame]24&eqos {
25 /delete-property/ assigned-clocks;
26 /delete-property/ assigned-clock-parents;
27 /delete-property/ assigned-clock-rates;
28};
29
30&ethphy0 {
31 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
32 reset-assert-us = <15000>;
33 reset-deassert-us = <100000>;
34};
35
36&fec {
37 phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
38 phy-reset-duration = <15>;
39 phy-reset-post-delay = <100>;
40};
41
42&flexspi {
43 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
44};
45
46&gpio1 {
47 bootph-pre-ram;
48};
49
50&gpio2 {
51 bootph-pre-ram;
52};
53
54&gpio3 {
55 bootph-pre-ram;
56};
57
58&gpio4 {
59 bootph-pre-ram;
60};
61
62&gpio5 {
63 bootph-pre-ram;
64};
65
66&i2c1 {
67 bootph-pre-ram;
68};
69
70&i2c2 {
71 bootph-pre-ram;
72};
73
74&i2c3 {
75 bootph-pre-ram;
76};
77
78&pca6416 {
79 compatible = "ti,tca6416";
80 label = "exp4";
81};
82
83&pca6416_1 {
84 compatible = "ti,tca6416";
85 label = "exp4";
86};
87
88&pca6416_3 {
89 compatible = "ti,tca6416";
90 label = "exp2";
91};
92
93&pinctrl_i2c1 {
94 bootph-pre-ram;
95};
96
97&pinctrl_pmic {
98 bootph-pre-ram;
99};
100
101&pinctrl_reg_usdhc2_vmmc {
102 bootph-pre-ram;
103};
104
105&pinctrl_uart2 {
106 bootph-pre-ram;
107};
108
109&pinctrl_usdhc2_gpio {
110 bootph-pre-ram;
111};
112
113&pinctrl_usdhc2 {
114 bootph-pre-ram;
115};
116
117&pinctrl_usdhc3 {
118 bootph-pre-ram;
119};
120
121&pinctrl_wdog {
122 bootph-pre-ram;
123};
124
125&reg_usdhc2_vmmc {
126 bootph-pre-ram;
127 u-boot,off-on-delay-us = <20000>;
128};
129
Adam Forda8554812023-03-23 22:06:16 -0500[diff] [blame]130&tpm {
131 compatible = "tcg,tpm_tis-spi";
132};
133
134&uart2 {
135 bootph-pre-ram;
136};
137
138&usdhc1 {
139 bootph-pre-ram;
140 assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
141 assigned-clock-rates = <400000000>;
142 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
143};
144
145&usdhc2 {
146 bootph-pre-ram;
147 sd-uhs-sdr104;
148 sd-uhs-ddr50;
149 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
150 assigned-clock-rates = <400000000>;
151 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
152};
153
154&usdhc3 {
155 bootph-pre-ram;
156 mmc-hs400-1_8v;
157 mmc-hs400-enhanced-strobe;
158 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
159 assigned-clock-rates = <400000000>;
160 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
161};
162
163&usb3_0 {
164 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
Adam Forda8554812023-03-23 22:06:16 -0500[diff] [blame]165};
166
167&usb3_1 {
168 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
Adam Forda8554812023-03-23 22:06:16 -0500[diff] [blame]169};
170
171&usb_dwc3_0 {
172 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
173 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
174 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
175 assigned-clock-rates = <400000000>;
176};
177
178&usb_dwc3_1 {
179 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
180 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
181 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
182 assigned-clock-rates = <400000000>;
183};
184
185&usdhc1 {
186 status = "disabled";
187};
188
189&wdog1 {
190 bootph-pre-ram;
191};