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git01.mediatek.com / filogic / uboot / 68bcfed9fdc2525894019938f5c26821614c9551 / . / arch / arm / dts / imx6qdl-gw5912.dtsi
blob: 7593872c07e8612f43249be0ee50d7274378b21f [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]17 nand = &gpmi;
18 usb0 = &usbh1;
19 usb1 = &usbotg;
20 };
21
22 chosen {
23 stdout-path = &uart2;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 user-pb {
32 label = "user_pb";
33 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
34 linux,code = <BTN_0>;
35 };
36
37 user-pb1x {
38 label = "user_pb1x";
39 linux,code = <BTN_1>;
40 interrupt-parent = <&gsc>;
41 interrupts = <0>;
42 };
43
44 key-erased {
45 label = "key-erased";
46 linux,code = <BTN_2>;
47 interrupt-parent = <&gsc>;
48 interrupts = <1>;
49 };
50
51 eeprom-wp {
52 label = "eeprom_wp";
53 linux,code = <BTN_3>;
54 interrupt-parent = <&gsc>;
55 interrupts = <2>;
56 };
57
58 tamper {
59 label = "tamper";
60 linux,code = <BTN_4>;
61 interrupt-parent = <&gsc>;
62 interrupts = <5>;
63 };
64
65 switch-hold {
66 label = "switch_hold";
67 linux,code = <BTN_5>;
68 interrupt-parent = <&gsc>;
69 interrupts = <7>;
70 };
71 };
72
73 leds {
74 compatible = "gpio-leds";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_gpio_leds>;
77
78 led0: user1 {
79 label = "user1";
80 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
81 default-state = "on";
82 linux,default-trigger = "heartbeat";
83 };
84
85 led1: user2 {
86 label = "user2";
87 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
88 default-state = "off";
89 };
90
91 led2: user3 {
92 label = "user3";
93 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
94 default-state = "off";
95 };
96 };
97
98 memory@10000000 {
99 device_type = "memory";
100 reg = <0x10000000 0x40000000>;
101 };
102
103 pps {
104 compatible = "pps-gpio";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_pps>;
107 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
108 };
109
110 reg_3p3v: regulator-3p3v {
111 compatible = "regulator-fixed";
112 regulator-name = "3P3V";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 regulator-always-on;
116 };
117
118 reg_usb_vbus: regulator-5p0v {
119 compatible = "regulator-fixed";
120 regulator-name = "usb_vbus";
121 regulator-min-microvolt = <5000000>;
122 regulator-max-microvolt = <5000000>;
123 regulator-always-on;
124 };
125};
126
127&can1 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_flexcan1>;
130 status = "okay";
131};
132
133&ecspi2 {
134 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_ecspi2>;
137 status = "okay";
138};
139
140&fec {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_enet>;
143 phy-mode = "rgmii-id";
144 status = "okay";
145};
146
147&gpmi {
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_gpmi_nand>;
150 status = "okay";
151};
152
153&i2c1 {
154 clock-frequency = <100000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_i2c1>;
157 status = "okay";
158
159 gsc: gsc@20 {
160 compatible = "gw,gsc";
161 reg = <0x20>;
162 interrupt-parent = <&gpio1>;
163 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
164 interrupt-controller;
165 #interrupt-cells = <1>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 adc {
170 compatible = "gw,gsc-adc";
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 channel@0 {
175 gw,mode = <0>;
176 reg = <0x00>;
177 label = "temp";
178 };
179
180 channel@2 {
181 gw,mode = <1>;
182 reg = <0x02>;
183 label = "vdd_vin";
184 };
185
186 channel@5 {
187 gw,mode = <1>;
188 reg = <0x05>;
189 label = "vdd_3p3";
190 };
191
192 channel@8 {
193 gw,mode = <1>;
194 reg = <0x08>;
195 label = "vdd_bat";
196 };
197
198 channel@b {
199 gw,mode = <1>;
200 reg = <0x0b>;
201 label = "vdd_5p0";
202 };
203
204 channel@e {
205 gw,mode = <1>;
206 reg = <0xe>;
207 label = "vdd_arm";
208 };
209
210 channel@11 {
211 gw,mode = <1>;
212 reg = <0x11>;
213 label = "vdd_soc";
214 };
215
216 channel@14 {
217 gw,mode = <1>;
218 reg = <0x14>;
219 label = "vdd_3p0";
220 };
221
222 channel@17 {
223 gw,mode = <1>;
224 reg = <0x17>;
225 label = "vdd_1p5";
226 };
227
228 channel@1d {
229 gw,mode = <1>;
230 reg = <0x1d>;
231 label = "vdd_1p8";
232 };
233
234 channel@20 {
235 gw,mode = <1>;
236 reg = <0x20>;
237 label = "vdd_1p0";
238 };
239
240 channel@23 {
241 gw,mode = <1>;
242 reg = <0x23>;
243 label = "vdd_2p5";
244 };
245 };
246
247 fan-controller@a {
248 compatible = "gw,gsc-fan";
249 #address-cells = <1>;
250 #size-cells = <0>;
251 reg = <0x0a>;
252 };
253 };
254
255 gsc_gpio: gpio@23 {
256 compatible = "nxp,pca9555";
257 reg = <0x23>;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-parent = <&gsc>;
261 interrupts = <4>;
262 };
263
264 eeprom@50 {
265 compatible = "atmel,24c02";
266 reg = <0x50>;
267 pagesize = <16>;
268 };
269
270 eeprom@51 {
271 compatible = "atmel,24c02";
272 reg = <0x51>;
273 pagesize = <16>;
274 };
275
276 eeprom@52 {
277 compatible = "atmel,24c02";
278 reg = <0x52>;
279 pagesize = <16>;
280 };
281
282 eeprom@53 {
283 compatible = "atmel,24c02";
284 reg = <0x53>;
285 pagesize = <16>;
286 };
287
288 rtc@68 {
289 compatible = "dallas,ds1672";
290 reg = <0x68>;
291 };
292};
293
294&i2c2 {
295 clock-frequency = <100000>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c2>;
298 status = "okay";
299};
300
301&i2c3 {
302 clock-frequency = <100000>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_i2c3>;
305 status = "okay";
306
307 accel@19 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_accel>;
310 compatible = "st,lis2de12";
311 reg = <0x19>;
312 st,drdy-int-pin = <1>;
313 interrupt-parent = <&gpio7>;
314 interrupts = <13 0>;
315 interrupt-names = "INT1";
316 };
317};
318
319&pcie {
320 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_pcie>;
322 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
323 status = "okay";
324};
325
326&pwm1 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
329 status = "disabled";
330};
331
332&pwm2 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
335 status = "disabled";
336};
337
338&pwm3 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
341 status = "disabled";
342};
343
344&pwm4 {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
347 status = "disabled";
348};
349
350&uart1 {
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_uart1>;
353 rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
354 status = "okay";
355};
356
357&uart2 {
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_uart2>;
360 status = "okay";
361};
362
363&uart5 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart5>;
366 status = "okay";
367};
368
369&usbotg {
370 vbus-supply = <&reg_usb_vbus>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usbotg>;
373 disable-over-current;
374 dr_mode = "host";
375 status = "okay";
376};
377
378&usbh1 {
379 vbus-supply = <&reg_usb_vbus>;
380 status = "okay";
381};
382
383&usdhc3 {
384 pinctrl-names = "default", "state_100mhz", "state_200mhz";
385 pinctrl-0 = <&pinctrl_usdhc3>;
386 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
387 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
388 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
389 vmmc-supply = <&reg_3p3v>;
390 no-1-8-v; /* firmware will remove if board revision supports */
391 status = "okay";
392};
393
394&wdog1 {
395 status = "disabled";
396};
397
398&wdog2 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_wdog>;
401 fsl,ext-reset-output;
402 status = "okay";
403};
404
405&iomuxc {
406 pinctrl_accel: accelmuxgrp {
407 fsl,pins = <
408 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
409 >;
410 };
411
412 pinctrl_enet: enetgrp {
413 fsl,pins = <
414 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
415 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
416 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
417 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
418 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
419 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
420 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
421 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
422 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
423 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
424 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
425 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
426 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
427 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
428 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
429 >;
430 };
431
432 pinctrl_ecspi2: escpi2grp {
433 fsl,pins = <
434 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
435 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
436 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
437 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
438 >;
439 };
440
441 pinctrl_flexcan1: flexcan1grp {
442 fsl,pins = <
443 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
444 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
445 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
446 >;
447 };
448
449 pinctrl_gpio_leds: gpioledsgrp {
450 fsl,pins = <
451 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
452 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
453 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
454 >;
455 };
456
457 pinctrl_gpmi_nand: gpminandgrp {
458 fsl,pins = <
459 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
460 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
461 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
462 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
463 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
464 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
465 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
466 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
467 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
468 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
469 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
470 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
471 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
472 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
473 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
474 >;
475 };
476
477 pinctrl_i2c1: i2c1grp {
478 fsl,pins = <
479 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
480 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
481 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
482 >;
483 };
484
485 pinctrl_i2c2: i2c2grp {
486 fsl,pins = <
487 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
488 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
489 >;
490 };
491
492 pinctrl_i2c3: i2c3grp {
493 fsl,pins = <
494 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
495 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
496 >;
497 };
498
499 pinctrl_pcie: pciegrp {
500 fsl,pins = <
501 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
502 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
503 >;
504 };
505
506 pinctrl_pps: ppsgrp {
507 fsl,pins = <
508 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
509 >;
510 };
511
512 pinctrl_pwm1: pwm1grp {
513 fsl,pins = <
514 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
515 >;
516 };
517
518 pinctrl_pwm2: pwm2grp {
519 fsl,pins = <
520 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
521 >;
522 };
523
524 pinctrl_pwm3: pwm3grp {
525 fsl,pins = <
526 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
527 >;
528 };
529
530 pinctrl_pwm4: pwm4grp {
531 fsl,pins = <
532 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
533 >;
534 };
535
536 pinctrl_uart1: uart1grp {
537 fsl,pins = <
538 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
539 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
540 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
541 >;
542 };
543
544 pinctrl_uart2: uart2grp {
545 fsl,pins = <
546 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
547 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
548 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
549 >;
550 };
551
552 pinctrl_uart5: uart5grp {
553 fsl,pins = <
554 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
555 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
556 >;
557 };
558
559 pinctrl_usbotg: usbotggrp {
560 fsl,pins = <
561 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
562 >;
563 };
564
565 pinctrl_usdhc3: usdhc3grp {
566 fsl,pins = <
567 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
568 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
569 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
570 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
571 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
572 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
573 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
574 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
575 >;
576 };
577
578 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
579 fsl,pins = <
580 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
581 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
582 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
583 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
584 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
585 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
586 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
587 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
588 >;
589 };
590
591 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
592 fsl,pins = <
593 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
594 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
595 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
596 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
597 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
598 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
599 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
600 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
601 >;
602 };
603
604 pinctrl_wdog: wdoggrp {
605 fsl,pins = <
606 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
607 >;
608 };
609};