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git01.mediatek.com / filogic / uboot / 68bcfed9fdc2525894019938f5c26821614c9551 / . / arch / arm / dts / imx6qdl-gw52xx.dtsi
blob: 6eedf8d40d87185f89338798d1062947edc25aa2 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]17 nand = &gpmi;
18 ssi0 = &ssi1;
19 usb0 = &usbh1;
20 usb1 = &usbotg;
21 };
22
23 chosen {
24 bootargs = "console=ttymxc1,115200";
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm4 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <7>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 user-pb {
40 label = "user_pb";
41 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
42 linux,code = <BTN_0>;
43 };
44
45 user-pb1x {
46 label = "user_pb1x";
47 linux,code = <BTN_1>;
48 interrupt-parent = <&gsc>;
49 interrupts = <0>;
50 };
51
52 key-erased {
53 label = "key-erased";
54 linux,code = <BTN_2>;
55 interrupt-parent = <&gsc>;
56 interrupts = <1>;
57 };
58
59 eeprom-wp {
60 label = "eeprom_wp";
61 linux,code = <BTN_3>;
62 interrupt-parent = <&gsc>;
63 interrupts = <2>;
64 };
65
66 tamper {
67 label = "tamper";
68 linux,code = <BTN_4>;
69 interrupt-parent = <&gsc>;
70 interrupts = <5>;
71 };
72
73 switch-hold {
74 label = "switch_hold";
75 linux,code = <BTN_5>;
76 interrupt-parent = <&gsc>;
77 interrupts = <7>;
78 };
79 };
80
81 leds {
82 compatible = "gpio-leds";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_gpio_leds>;
85
86 led0: user1 {
87 label = "user1";
88 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
89 default-state = "on";
90 linux,default-trigger = "heartbeat";
91 };
92
93 led1: user2 {
94 label = "user2";
95 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
96 default-state = "off";
97 };
98
99 led2: user3 {
100 label = "user3";
101 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
102 default-state = "off";
103 };
104 };
105
106 memory@10000000 {
107 device_type = "memory";
108 reg = <0x10000000 0x20000000>;
109 };
110
111 pps {
112 compatible = "pps-gpio";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_pps>;
115 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
116 status = "okay";
117 };
118
119 reg_1p0v: regulator-1p0v {
120 compatible = "regulator-fixed";
121 regulator-name = "1P0V";
122 regulator-min-microvolt = <1000000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-always-on;
125 };
126
127 reg_3p3v: regulator-3p3v {
128 compatible = "regulator-fixed";
129 regulator-name = "3P3V";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 regulator-always-on;
133 };
134
135 reg_5p0v: regulator-5p0v {
136 compatible = "regulator-fixed";
137 regulator-name = "5P0V";
138 regulator-min-microvolt = <5000000>;
139 regulator-max-microvolt = <5000000>;
140 regulator-always-on;
141 };
142
143 reg_usb_otg_vbus: regulator-usb-otg-vbus {
144 compatible = "regulator-fixed";
145 regulator-name = "usb_otg_vbus";
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5000000>;
148 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
149 enable-active-high;
150 };
151
152 sound {
153 compatible = "fsl,imx6q-ventana-sgtl5000",
154 "fsl,imx-audio-sgtl5000";
155 model = "sgtl5000-audio";
156 ssi-controller = <&ssi1>;
157 audio-codec = <&codec>;
158 audio-routing =
159 "MIC_IN", "Mic Jack",
160 "Mic Jack", "Mic Bias",
161 "Headphone Jack", "HP_OUT";
162 mux-int-port = <1>;
163 mux-ext-port = <4>;
164 };
165};
166
167&audmux {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_audmux>;
170 status = "okay";
171};
172
173&can1 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_flexcan1>;
176 status = "okay";
177};
178
179&clks {
180 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
181 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
182 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
183 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
184};
185
186&ecspi3 {
187 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_ecspi3>;
190 status = "okay";
191};
192
193&fec {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_enet>;
196 phy-mode = "rgmii-id";
197 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
198 status = "okay";
199};
200
201&gpmi {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_gpmi_nand>;
204 status = "okay";
205};
206
207&hdmi {
208 ddc-i2c-bus = <&i2c3>;
209 status = "okay";
210};
211
212&i2c1 {
213 clock-frequency = <100000>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c1>;
216 status = "okay";
217
218 gsc: gsc@20 {
219 compatible = "gw,gsc";
220 reg = <0x20>;
221 interrupt-parent = <&gpio1>;
222 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
223 interrupt-controller;
224 #interrupt-cells = <1>;
225 #size-cells = <0>;
226
227 adc {
228 compatible = "gw,gsc-adc";
229 #address-cells = <1>;
230 #size-cells = <0>;
231
232 channel@0 {
233 gw,mode = <0>;
234 reg = <0x00>;
235 label = "temp";
236 };
237
238 channel@2 {
239 gw,mode = <1>;
240 reg = <0x02>;
241 label = "vdd_vin";
242 };
243
244 channel@5 {
245 gw,mode = <1>;
246 reg = <0x05>;
247 label = "vdd_3p3";
248 };
249
250 channel@8 {
251 gw,mode = <1>;
252 reg = <0x08>;
253 label = "vdd_bat";
254 };
255
256 channel@b {
257 gw,mode = <1>;
258 reg = <0x0b>;
259 label = "vdd_5p0";
260 };
261
262 channel@e {
263 gw,mode = <1>;
264 reg = <0xe>;
265 label = "vdd_arm";
266 };
267
268 channel@11 {
269 gw,mode = <1>;
270 reg = <0x11>;
271 label = "vdd_soc";
272 };
273
274 channel@14 {
275 gw,mode = <1>;
276 reg = <0x14>;
277 label = "vdd_3p0";
278 };
279
280 channel@17 {
281 gw,mode = <1>;
282 reg = <0x17>;
283 label = "vdd_1p5";
284 };
285
286 channel@1d {
287 gw,mode = <1>;
288 reg = <0x1d>;
289 label = "vdd_1p8";
290 };
291
292 channel@20 {
293 gw,mode = <1>;
294 reg = <0x20>;
295 label = "vdd_1p0";
296 };
297
298 channel@23 {
299 gw,mode = <1>;
300 reg = <0x23>;
301 label = "vdd_2p5";
302 };
303
304 channel@29 {
305 gw,mode = <1>;
306 reg = <0x29>;
307 label = "vdd_an1";
308 };
309 };
310 };
311
312 gsc_gpio: gpio@23 {
313 compatible = "nxp,pca9555";
314 reg = <0x23>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 interrupt-parent = <&gsc>;
318 interrupts = <4>;
319 };
320
321 eeprom1: eeprom@50 {
322 compatible = "atmel,24c02";
323 reg = <0x50>;
324 pagesize = <16>;
325 };
326
327 eeprom2: eeprom@51 {
328 compatible = "atmel,24c02";
329 reg = <0x51>;
330 pagesize = <16>;
331 };
332
333 eeprom3: eeprom@52 {
334 compatible = "atmel,24c02";
335 reg = <0x52>;
336 pagesize = <16>;
337 };
338
339 eeprom4: eeprom@53 {
340 compatible = "atmel,24c02";
341 reg = <0x53>;
342 pagesize = <16>;
343 };
344
345 rtc: ds1672@68 {
346 compatible = "dallas,ds1672";
347 reg = <0x68>;
348 };
349};
350
351&i2c2 {
352 clock-frequency = <100000>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_i2c2>;
355 status = "okay";
356
357 ltc3676: pmic@3c {
358 compatible = "lltc,ltc3676";
359 reg = <0x3c>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_pmic>;
362 interrupt-parent = <&gpio1>;
363 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
364
365 regulators {
366 /* VDD_SOC (1+R1/R2 = 1.635) */
367 reg_vdd_soc: sw1 {
368 regulator-name = "vddsoc";
369 regulator-min-microvolt = <674400>;
370 regulator-max-microvolt = <1308000>;
371 lltc,fb-voltage-divider = <127000 200000>;
372 regulator-ramp-delay = <7000>;
373 regulator-boot-on;
374 regulator-always-on;
375 };
376
377 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
378 reg_1p8v: sw2 {
379 regulator-name = "vdd1p8";
380 regulator-min-microvolt = <1033310>;
381 regulator-max-microvolt = <2004000>;
382 lltc,fb-voltage-divider = <301000 200000>;
383 regulator-ramp-delay = <7000>;
384 regulator-boot-on;
385 regulator-always-on;
386 };
387
388 /* VDD_ARM (1+R1/R2 = 1.635) */
389 reg_vdd_arm: sw3 {
390 regulator-name = "vddarm";
391 regulator-min-microvolt = <674400>;
392 regulator-max-microvolt = <1308000>;
393 lltc,fb-voltage-divider = <127000 200000>;
394 regulator-ramp-delay = <7000>;
395 regulator-boot-on;
396 regulator-always-on;
397 };
398
399 /* VDD_DDR (1+R1/R2 = 2.105) */
400 reg_vdd_ddr: sw4 {
401 regulator-name = "vddddr";
402 regulator-min-microvolt = <868310>;
403 regulator-max-microvolt = <1684000>;
404 lltc,fb-voltage-divider = <221000 200000>;
405 regulator-ramp-delay = <7000>;
406 regulator-boot-on;
407 regulator-always-on;
408 };
409
410 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
411 reg_2p5v: ldo2 {
412 regulator-name = "vdd2p5";
413 regulator-min-microvolt = <2490375>;
414 regulator-max-microvolt = <2490375>;
415 lltc,fb-voltage-divider = <487000 200000>;
416 regulator-boot-on;
417 regulator-always-on;
418 };
419
420 /* VDD_AUD_1P8: Audio codec */
421 reg_aud_1p8v: ldo3 {
422 regulator-name = "vdd1p8a";
423 regulator-min-microvolt = <1800000>;
424 regulator-max-microvolt = <1800000>;
425 regulator-boot-on;
426 };
427
428 /* VDD_HIGH (1+R1/R2 = 4.17) */
429 reg_3p0v: ldo4 {
430 regulator-name = "vdd3p0";
431 regulator-min-microvolt = <3023250>;
432 regulator-max-microvolt = <3023250>;
433 lltc,fb-voltage-divider = <634000 200000>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437 };
438 };
439};
440
441&i2c3 {
442 clock-frequency = <100000>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_i2c3>;
445 status = "okay";
446
447 codec: sgtl5000@a {
448 compatible = "fsl,sgtl5000";
449 reg = <0x0a>;
450 clocks = <&clks IMX6QDL_CLK_CKO>;
451 VDDA-supply = <&reg_1p8v>;
452 VDDIO-supply = <&reg_3p3v>;
453 };
454
455 touchscreen: egalax_ts@4 {
456 compatible = "eeti,egalax_ts";
457 reg = <0x04>;
458 interrupt-parent = <&gpio7>;
459 interrupts = <12 2>;
460 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
461 };
462
463 accel@1e {
464 compatible = "nxp,fxos8700";
465 reg = <0x1e>;
466 };
467};
468
469&ldb {
470 status = "okay";
471
472 lvds-channel@0 {
473 fsl,data-mapping = "spwg";
474 fsl,data-width = <18>;
475 status = "okay";
476
477 display-timings {
478 native-mode = <&timing0>;
479 timing0: hsd100pxn1 {
480 clock-frequency = <65000000>;
481 hactive = <1024>;
482 vactive = <768>;
483 hback-porch = <220>;
484 hfront-porch = <40>;
485 vback-porch = <21>;
486 vfront-porch = <7>;
487 hsync-len = <60>;
488 vsync-len = <10>;
489 };
490 };
491 };
492};
493
494&pcie {
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_pcie>;
497 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
498 status = "okay";
499};
500
501&pwm2 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
504 status = "disabled";
505};
506
507&pwm3 {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
510 status = "disabled";
511};
512
513&pwm4 {
514 #pwm-cells = <2>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_pwm4>;
517 status = "okay";
518};
519
520&ssi1 {
521 status = "okay";
522};
523
524&uart1 {
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_uart1>;
527 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
528 status = "okay";
529};
530
531&uart2 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_uart2>;
534 status = "okay";
535};
536
537&uart5 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart5>;
540 status = "okay";
541};
542
543&usbotg {
544 vbus-supply = <&reg_usb_otg_vbus>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_usbotg>;
547 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]548 dr_mode = "otg";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]549 status = "okay";
550};
551
552&usbh1 {
553 status = "okay";
554};
555
556&usdhc3 {
557 pinctrl-names = "default", "state_100mhz", "state_200mhz";
558 pinctrl-0 = <&pinctrl_usdhc3>;
559 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
560 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
561 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
562 vmmc-supply = <&reg_3p3v>;
563 no-1-8-v; /* firmware will remove if board revision supports */
564 status = "okay";
565};
566
567&wdog1 {
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_wdog>;
570 fsl,ext-reset-output;
571};
572
573&iomuxc {
574 pinctrl_audmux: audmuxgrp {
575 fsl,pins = <
576 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
577 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
578 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
579 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
580 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
581 >;
582 };
583
584 pinctrl_ecspi3: escpi3grp {
585 fsl,pins = <
586 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
587 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
588 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
589 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
590 >;
591 };
592
593 pinctrl_enet: enetgrp {
594 fsl,pins = <
595 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
596 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
597 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
598 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
599 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
600 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
601 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
602 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
603 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
604 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
605 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
606 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
607 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
608 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
609 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
610 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
611 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
612 >;
613 };
614
615 pinctrl_flexcan1: flexcan1grp {
616 fsl,pins = <
617 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
618 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
619 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
620 >;
621 };
622
623 pinctrl_gpio_leds: gpioledsgrp {
624 fsl,pins = <
625 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
626 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
627 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
628 >;
629 };
630
631 pinctrl_gpmi_nand: gpminandgrp {
632 fsl,pins = <
633 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
634 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
635 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
636 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
637 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
638 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
639 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
640 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
641 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
642 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
643 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
644 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
645 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
646 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
647 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
648 >;
649 };
650
651 pinctrl_i2c1: i2c1grp {
652 fsl,pins = <
653 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
654 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
655 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
656 >;
657 };
658
659 pinctrl_i2c2: i2c2grp {
660 fsl,pins = <
661 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
662 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
663 >;
664 };
665
666 pinctrl_i2c3: i2c3grp {
667 fsl,pins = <
668 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
669 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
670 >;
671 };
672
673 pinctrl_pcie: pciegrp {
674 fsl,pins = <
675 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
676 >;
677 };
678
679 pinctrl_pmic: pmicgrp {
680 fsl,pins = <
681 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
682 >;
683 };
684
685 pinctrl_pps: ppsgrp {
686 fsl,pins = <
687 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
688 >;
689 };
690
691 pinctrl_pwm2: pwm2grp {
692 fsl,pins = <
693 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
694 >;
695 };
696
697 pinctrl_pwm3: pwm3grp {
698 fsl,pins = <
699 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
700 >;
701 };
702
703 pinctrl_pwm4: pwm4grp {
704 fsl,pins = <
705 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
706 >;
707 };
708
709 pinctrl_uart1: uart1grp {
710 fsl,pins = <
711 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
712 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
713 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
714 >;
715 };
716
717 pinctrl_uart2: uart2grp {
718 fsl,pins = <
719 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
720 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
721 >;
722 };
723
724 pinctrl_uart5: uart5grp {
725 fsl,pins = <
726 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
727 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
728 >;
729 };
730
731 pinctrl_usbotg: usbotggrp {
732 fsl,pins = <
733 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
734 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
735 >;
736 };
737
738 pinctrl_usdhc3: usdhc3grp {
739 fsl,pins = <
740 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
741 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
742 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
743 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
744 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
745 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
746 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
747 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
748 >;
749 };
750
751 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
752 fsl,pins = <
753 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
754 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
755 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
756 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
757 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
758 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
759 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
760 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
761 >;
762 };
763
764 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
765 fsl,pins = <
766 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
767 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
768 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
769 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
770 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
771 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
772 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
773 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
774 >;
775 };
776
777 pinctrl_wdog: wdoggrp {
778 fsl,pins = <
779 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
780 >;
781 };
782};