blob: 4fed2215365cf2d0585cc5d3cb4b5e2e4b9a80c9 [file] [log] [blame]
Michal Simekb40e5b62015-07-22 11:39:04 +02001/*
2 * Xilinx ZC770 XM013 board DTS
3 *
4 * Copyright (C) 2013 Xilinx, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10/ {
11 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
12 model = "Xilinx Zynq";
13
14 aliases {
15 i2c0 = &i2c1;
16 serial0 = &uart1;
17 spi0 = &spi0;
18 };
19
20 chosen {
Michal Simekc9af95a2016-01-12 13:56:44 +010021 bootargs = "root=/dev/ram rw earlyprintk";
22 stdout-path = "serial0:115200n8";
Michal Simekb40e5b62015-07-22 11:39:04 +020023 };
24
Michal Simeka8d362f2015-08-12 11:25:05 +020025 memory {
Michal Simekb40e5b62015-07-22 11:39:04 +020026 device_type = "memory";
27 reg = <0x0 0x40000000>;
28 };
29
30 usb_phy1: phy1 {
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
33 };
34};
35
Michal Simekb40e5b62015-07-22 11:39:04 +020036&can0 {
37 status = "okay";
38};
39
40&i2c1 {
41 status = "okay";
42 clock-frequency = <400000>;
43
44 m24c02_eeprom@52 {
45 compatible = "at,24c02";
46 reg = <0x52>;
47 };
48};
49
Michal Simek49f44b92016-01-14 13:09:16 +010050&spi0 {
51 status = "okay";
52 num-cs = <4>;
53 is-decoded-cs = <0>;
54};
55
Michal Simekb40e5b62015-07-22 11:39:04 +020056&uart1 {
Simon Glass8c7323a2015-10-17 19:41:24 -060057 u-boot,dm-pre-reloc;
Michal Simekb40e5b62015-07-22 11:39:04 +020058 status = "okay";
59};
60
61&usb1 {
62 status = "okay";
63 dr_mode = "host";
64 usb-phy = <&usb_phy1>;
65};