Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015, Savoir-faire Linux Inc. |
| 4 | * |
| 5 | * Derived from MX51EVK code by |
| 6 | * Guennadi Liakhovetski <lg@denx.de> |
| 7 | * Freescale Semiconductor, Inc. |
| 8 | * |
| 9 | * Configuration settings for the TS4800 Board |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /* High Level Configuration Options */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 16 | |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 17 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 18 | |
| 19 | #define CONFIG_HW_WATCHDOG |
| 20 | |
Tom Rini | 4815734 | 2017-01-25 20:42:35 -0500 | [diff] [blame] | 21 | #define CONFIG_MACH_TYPE MACH_TYPE_TS48XX |
| 22 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 23 | /* text base address used when linking */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 24 | |
| 25 | #include <asm/arch/imx-regs.h> |
| 26 | |
| 27 | /* enable passing of ATAGs */ |
| 28 | #define CONFIG_CMDLINE_TAG |
| 29 | #define CONFIG_SETUP_MEMORY_TAGS |
| 30 | #define CONFIG_INITRD_TAG |
| 31 | #define CONFIG_REVISION_TAG |
| 32 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 33 | /* |
| 34 | * Size of malloc() pool |
| 35 | */ |
| 36 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| 37 | |
| 38 | /* |
| 39 | * Hardware drivers |
| 40 | */ |
| 41 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 42 | #define CONFIG_MXC_UART_BASE UART1_BASE |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 43 | |
| 44 | /* |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 45 | * MMC Configs |
| 46 | * */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 47 | #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR |
| 48 | |
Damien Riegel | 4013711 | 2015-06-30 17:17:48 -0400 | [diff] [blame] | 49 | /* |
| 50 | * Eth Configs |
| 51 | */ |
Damien Riegel | 4013711 | 2015-06-30 17:17:48 -0400 | [diff] [blame] | 52 | |
| 53 | #define CONFIG_FEC_MXC |
| 54 | #define IMX_FEC_BASE FEC_BASE_ADDR |
| 55 | #define CONFIG_ETHPRIME "FEC" |
| 56 | #define CONFIG_FEC_MXC_PHYADDR 0 |
| 57 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 58 | /* allow to overwrite serial and ethaddr */ |
| 59 | #define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 60 | |
| 61 | /*********************************************************** |
| 62 | * Command definition |
| 63 | ***********************************************************/ |
| 64 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 65 | /* Environment variables */ |
| 66 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 67 | |
| 68 | #define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ |
| 69 | |
| 70 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 71 | "script=boot.scr\0" \ |
Damien Riegel | 191ed22 | 2016-04-21 17:34:02 -0400 | [diff] [blame] | 72 | "image=zImage\0" \ |
| 73 | "fdt_file=imx51-ts4800.dtb\0" \ |
| 74 | "fdt_addr=0x90fe0000\0" \ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 75 | "mmcdev=0\0" \ |
Damien Riegel | 191ed22 | 2016-04-21 17:34:02 -0400 | [diff] [blame] | 76 | "mmcpart=2\0" \ |
| 77 | "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ |
| 78 | "mmcargs=setenv bootargs root=${mmcroot}\0" \ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 79 | "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ |
| 80 | "loadbootscript=" \ |
| 81 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
| 82 | "bootscript=echo Running bootscript from mmc ...; " \ |
| 83 | "source\0" \ |
| 84 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ |
Damien Riegel | 191ed22 | 2016-04-21 17:34:02 -0400 | [diff] [blame] | 85 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 86 | "mmcboot=echo Booting from mmc ...; " \ |
| 87 | "run mmcargs addtty; " \ |
Damien Riegel | 191ed22 | 2016-04-21 17:34:02 -0400 | [diff] [blame] | 88 | "if run loadfdt; then " \ |
| 89 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
| 90 | "else " \ |
| 91 | "echo ERR: cannot load FDT; " \ |
| 92 | "fi; " |
| 93 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 94 | |
| 95 | #define CONFIG_BOOTCOMMAND \ |
| 96 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
| 97 | "if run loadbootscript; then " \ |
| 98 | "run bootscript; " \ |
| 99 | "else " \ |
| 100 | "if run loadimage; then " \ |
| 101 | "run mmcboot; " \ |
| 102 | "fi; " \ |
| 103 | "fi; " \ |
| 104 | "fi; " |
| 105 | |
| 106 | /* |
| 107 | * Miscellaneous configurable options |
| 108 | */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 109 | |
| 110 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 111 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 112 | /*----------------------------------------------------------------------- |
| 113 | * Physical Memory Map |
| 114 | */ |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 115 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
| 116 | #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) |
| 117 | |
| 118 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
| 119 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
| 120 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
| 121 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 122 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 123 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 124 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 125 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 126 | |
| 127 | /* Low level init */ |
| 128 | #define CONFIG_SYS_DDR_CLKSEL 0 |
| 129 | #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 |
| 130 | #define CONFIG_SYS_MAIN_PWR_ON |
| 131 | |
| 132 | /*----------------------------------------------------------------------- |
| 133 | * Environment organization |
| 134 | */ |
| 135 | |
Lucile Quirion | a84f6f9 | 2015-06-30 17:17:47 -0400 | [diff] [blame] | 136 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 137 | |
| 138 | #endif |