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git01.mediatek.com / filogic / uboot / 676f595bb80c2268892d3dc6b43e8eff409bb29e / . / arch / arm / imx-common / speed.c
blob: 26132bf71daac8924b663841b494fe4523e8449d [file] [log] [blame]
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]9 */
10
11#include <common.h>
12#include <asm/arch/imx-regs.h>
Stefano Babicac41d4d2010-03-05 17:54:37 +0100[diff] [blame]13#include <asm/arch/clock.h>
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]14
John Rigby0d21ed02010-12-20 18:27:51 -0700[diff] [blame]15#ifdef CONFIG_FSL_ESDHC
16DECLARE_GLOBAL_DATA_PTR;
17#endif
18
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]19int get_clocks(void)
20{
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]21#ifdef CONFIG_FSL_ESDHC
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]22#ifdef CONFIG_FSL_USDHC
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]23#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]24 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]25#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]26 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]27#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]28 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]29#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]30 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]31#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]32#else
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]33#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]34 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]35#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]36 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]37#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]38 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]39#else
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]40 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
Benoît Thébaudeaueb9c2552012-09-27 10:24:37 +0000[diff] [blame]41#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]42#endif
Michael Langerb2ec8162012-06-14 03:44:33 +0000[diff] [blame]43#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100[diff] [blame]44 return 0;
45}