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Tom Rini10e47792018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00002#
3# (C) Copyright 2000-2003
4# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5#
Ley Foon Tan5b7cea62017-04-26 02:44:48 +08006# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00007
Ley Foon Tan5b7cea62017-04-26 02:44:48 +08008obj-y += board.o
9obj-y += clock_manager.o
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080010obj-y += misc.o
11obj-y += reset_manager.o
12obj-y += timer.o
Dinh Nguyen9365e902015-12-02 13:31:32 -060013
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080014ifdef CONFIG_TARGET_SOCFPGA_GEN5
15obj-y += clock_manager_gen5.o
16obj-y += misc_gen5.o
17obj-y += reset_manager_gen5.o
18obj-y += scan_manager.o
19obj-y += system_manager_gen5.o
20obj-y += wrap_pll_config.o
Tien Fong Chee31e50f42017-07-26 13:05:38 +080021obj-y += fpga_manager.o
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080022endif
Ley Foon Tan778ed2c2017-04-26 02:44:38 +080023
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080024ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
25obj-y += clock_manager_arria10.o
26obj-y += misc_arria10.o
27obj-y += pinmux_arria10.o
28obj-y += reset_manager_arria10.o
29endif
Marek Vasutaefb78d2015-08-02 21:12:09 +020030
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080031ifdef CONFIG_SPL_BUILD
32obj-y += spl.o
33ifdef CONFIG_TARGET_SOCFPGA_GEN5
34obj-y += freeze_controller.o
35obj-y += wrap_iocsr_config.o
36obj-y += wrap_pinmux_config.o
37obj-y += wrap_sdram_config.o
38endif
39endif
40
41ifdef CONFIG_TARGET_SOCFPGA_GEN5
Marek Vasutaefb78d2015-08-02 21:12:09 +020042# QTS-generated config file wrappers
Marek Vasutaefb78d2015-08-02 21:12:09 +020043CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
44CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
45CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
46CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080047endif