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Tom Rini8b0c8a12018-05-06 18:27:01 -04001/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Patrick Delaunay01e3afe2018-03-19 19:09:21 +01002/*
3 * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
Patrick Delaunay01e3afe2018-03-19 19:09:21 +01004 */
5
Patrick Delaunay123687c2022-05-20 18:24:46 +02006/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
Patrick Delaunay45c82d22019-02-27 17:01:13 +01007#define CPU_STM32MP157Cxx 0x05000000
8#define CPU_STM32MP157Axx 0x05000001
9#define CPU_STM32MP153Cxx 0x05000024
10#define CPU_STM32MP153Axx 0x05000025
11#define CPU_STM32MP151Cxx 0x0500002E
12#define CPU_STM32MP151Axx 0x0500002F
Patrick Delaunaydb33b0e2020-02-26 11:26:43 +010013#define CPU_STM32MP157Fxx 0x05000080
14#define CPU_STM32MP157Dxx 0x05000081
15#define CPU_STM32MP153Fxx 0x050000A4
16#define CPU_STM32MP153Dxx 0x050000A5
17#define CPU_STM32MP151Fxx 0x050000AE
18#define CPU_STM32MP151Dxx 0x050000AF
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010019
Patrick Delaunay123687c2022-05-20 18:24:46 +020020#define CPU_STM32MP135Cxx 0x05010000
21#define CPU_STM32MP135Axx 0x05010001
22#define CPU_STM32MP133Cxx 0x050100C0
23#define CPU_STM32MP133Axx 0x050100C1
24#define CPU_STM32MP131Cxx 0x050106C8
25#define CPU_STM32MP131Axx 0x050106C9
26#define CPU_STM32MP135Fxx 0x05010800
27#define CPU_STM32MP135Dxx 0x05010801
28#define CPU_STM32MP133Fxx 0x050108C0
29#define CPU_STM32MP133Dxx 0x050108C1
30#define CPU_STM32MP131Fxx 0x05010EC8
31#define CPU_STM32MP131Dxx 0x05010EC9
32
Patrick Delaunay45c82d22019-02-27 17:01:13 +010033/* return CPU_STMP32MP...Xxx constants */
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010034u32 get_cpu_type(void);
35
Patrick Delaunay79bc6402020-03-18 09:24:48 +010036#define CPU_DEV_STM32MP15 0x500
Patrick Delaunay123687c2022-05-20 18:24:46 +020037#define CPU_DEV_STM32MP13 0x501
Patrick Delaunay79bc6402020-03-18 09:24:48 +010038
39/* return CPU_DEV constants */
40u32 get_cpu_dev(void);
41
Patrick Delaunay92033592022-04-15 15:00:43 +020042#define CPU_REV1 0x1000
43#define CPU_REV1_1 0x1001
44#define CPU_REV2 0x2000
45#define CPU_REV2_1 0x2001
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010046
Patrick Delaunay92033592022-04-15 15:00:43 +020047/* return Silicon revision = REV_ID[15:0] of Device Version */
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010048u32 get_cpu_rev(void);
Patrick Delaunayc74d6342019-07-05 17:20:13 +020049
50/* Get Package options from OTP */
51u32 get_cpu_package(void);
52
Patrick Delaunaye4bdd542022-05-20 18:24:42 +020053/* package used for STM32MP15x */
54#define STM32MP15_PKG_AA_LBGA448 4
55#define STM32MP15_PKG_AB_LBGA354 3
56#define STM32MP15_PKG_AC_TFBGA361 2
57#define STM32MP15_PKG_AD_TFBGA257 1
58#define STM32MP15_PKG_UNKNOWN 0
Patrick Delaunayc74d6342019-07-05 17:20:13 +020059
Patrick Delaunay3e738f22020-02-12 19:37:43 +010060/* Get SOC name */
61#define SOC_NAME_SIZE 20
62void get_soc_name(char name[SOC_NAME_SIZE]);
63
Patrick Delaunay18660a62019-02-27 17:01:12 +010064/* return boot mode */
65u32 get_bootmode(void);
Marek Vasut187cae22019-12-18 16:52:19 +010066
67int setup_mac_address(void);
Patrick Delaunay3d1fe4e2020-05-25 12:19:45 +020068
69/* board power management : configure vddcore according OPP */
70void board_vddcore_init(u32 voltage_mv);
Patrick Delaunay9fa24a52022-05-20 18:24:41 +020071
Patrick Delaunaye4bdd542022-05-20 18:24:42 +020072/* weak function */
73void stm32mp_cpu_init(void);
74void stm32mp_misc_init(void);
75
Patrick Delaunay9fa24a52022-05-20 18:24:41 +020076/* helper function: read data from OTP */
77u32 get_otp(int index, int shift, int mask);