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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sedji Gaouaou538566d2009-07-09 10:16:29 +02002/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Sedji Gaouaou538566d2009-07-09 10:16:29 +02005 * Lead Tech Design <www.leadtechdesign.com>
Sedji Gaouaou538566d2009-07-09 10:16:29 +02006 */
7
8#include <common.h>
Wenyou Yangcf6667c2017-04-18 15:15:50 +08009#include <debug_uart.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070010#include <vsprintf.h>
Thomas Petazzonia5e85762011-08-04 11:08:50 +000011#include <asm/io.h>
Bo Shenc56e9f42015-03-27 14:23:34 +080012#include <asm/arch/clk.h>
Thomas Petazzonia5e85762011-08-04 11:08:50 +000013#include <asm/arch/at91sam9g45_matrix.h>
Sedji Gaouaou538566d2009-07-09 10:16:29 +020014#include <asm/arch/at91sam9_smc.h>
15#include <asm/arch/at91_common.h>
Sedji Gaouaou538566d2009-07-09 10:16:29 +020016#include <asm/arch/gpio.h>
Thomas Petazzonia5e85762011-08-04 11:08:50 +000017#include <asm/arch/clk.h>
Sedji Gaouaou538566d2009-07-09 10:16:29 +020018#include <lcd.h>
Masahiro Yamada2b7a8732017-11-30 13:45:24 +090019#include <linux/mtd/rawnand.h>
Sedji Gaouaou538566d2009-07-09 10:16:29 +020020#include <atmel_lcdc.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060021#include <asm/mach-types.h>
Sedji Gaouaou538566d2009-07-09 10:16:29 +020022
23DECLARE_GLOBAL_DATA_PTR;
24
25/* ------------------------------------------------------------------------- */
26/*
27 * Miscelaneous platform dependent initialisations
28 */
29
30#ifdef CONFIG_CMD_NAND
Thomas Petazzonia5e85762011-08-04 11:08:50 +000031void at91sam9m10g45ek_nand_hw_init(void)
Sedji Gaouaou538566d2009-07-09 10:16:29 +020032{
Thomas Petazzonia5e85762011-08-04 11:08:50 +000033 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
34 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
Sedji Gaouaou538566d2009-07-09 10:16:29 +020035 unsigned long csa;
36
37 /* Enable CS3 */
Thomas Petazzonia5e85762011-08-04 11:08:50 +000038 csa = readl(&matrix->ebicsa);
39 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
40 writel(csa, &matrix->ebicsa);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020041
42 /* Configure SMC CS3 for NAND/SmartMedia */
Thomas Petazzonia5e85762011-08-04 11:08:50 +000043 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
44 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
45 &smc->cs[3].setup);
46 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
47 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
48 &smc->cs[3].pulse);
49 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
50 &smc->cs[3].cycle);
51 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
52 AT91_SMC_MODE_EXNW_DISABLE |
Sedji Gaouaou538566d2009-07-09 10:16:29 +020053#ifdef CONFIG_SYS_NAND_DBW_16
Thomas Petazzonia5e85762011-08-04 11:08:50 +000054 AT91_SMC_MODE_DBW_16 |
Sedji Gaouaou538566d2009-07-09 10:16:29 +020055#else /* CONFIG_SYS_NAND_DBW_8 */
Thomas Petazzonia5e85762011-08-04 11:08:50 +000056 AT91_SMC_MODE_DBW_8 |
Sedji Gaouaou538566d2009-07-09 10:16:29 +020057#endif
Thomas Petazzonia5e85762011-08-04 11:08:50 +000058 AT91_SMC_MODE_TDF_CYCLE(3),
59 &smc->cs[3].mode);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020060
Wenyou Yang78f89762016-02-03 10:16:50 +080061 at91_periph_clk_enable(ATMEL_ID_PIOC);
Sedji Gaouaou538566d2009-07-09 10:16:29 +020062
63 /* Configure RDY/BSY */
64 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
65
66 /* Enable NandFlash */
67 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
68}
69#endif
70
Bo Shenc56e9f42015-03-27 14:23:34 +080071#if defined(CONFIG_SPL_BUILD)
72#include <spl.h>
73#include <nand.h>
74
75void at91_spl_board_init(void)
76{
77 /*
78 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
79 * test mode, so it needs do some action to exit test mode.
80 */
81 at91_periph_clk_enable(ATMEL_ID_PIODE);
82 at91_set_gpio_output(AT91_PIN_PD7, 0);
83 at91_set_gpio_output(AT91_PIN_PD8, 0);
84 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
85 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
86
Wenyou Yange035ea72017-09-14 11:07:44 +080087#ifdef CONFIG_SD_BOOT
Bo Shenc56e9f42015-03-27 14:23:34 +080088 at91_mci_hw_init();
Wenyou Yange035ea72017-09-14 11:07:44 +080089#elif CONFIG_NAND_BOOT
Bo Shenc56e9f42015-03-27 14:23:34 +080090 at91sam9m10g45ek_nand_hw_init();
91#endif
92}
93
94#include <asm/arch/atmel_mpddrc.h>
Wenyou Yangaa0a58d2016-02-01 18:12:15 +080095static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
Bo Shenc56e9f42015-03-27 14:23:34 +080096{
97 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
98
99 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
100 ATMEL_MPDDRC_CR_NR_ROW_14 |
101 ATMEL_MPDDRC_CR_DQMS_SHARED |
102 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
103
104 ddr2->rtr = 0x24b;
105
106 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
107 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
108 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
109 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
110 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
111 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
112 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
113 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
114
115 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
116 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
117 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
118 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
119
120 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
121 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
122 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
123 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
124}
125
126void mem_init(void)
127{
Wenyou Yangaa0a58d2016-02-01 18:12:15 +0800128 struct atmel_mpddrc_config ddr2;
Bo Shenc56e9f42015-03-27 14:23:34 +0800129
130 ddr2_conf(&ddr2);
131
Wenyou Yang78f89762016-02-03 10:16:50 +0800132 at91_system_clk_enable(AT91_PMC_DDR);
Bo Shenc56e9f42015-03-27 14:23:34 +0800133
Bo Shenc56e9f42015-03-27 14:23:34 +0800134 /* DDRAM2 Controller initialize */
Erik van Luijk59d780a2015-08-13 15:43:18 +0200135 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
Bo Shenc56e9f42015-03-27 14:23:34 +0800136}
137#endif
138
Sergey Matyukevichd25010d2010-06-09 23:09:06 +0400139#ifdef CONFIG_CMD_USB
140static void at91sam9m10g45ek_usb_hw_init(void)
141{
Wenyou Yang78f89762016-02-03 10:16:50 +0800142 at91_periph_clk_enable(ATMEL_ID_PIODE);
Sergey Matyukevichd25010d2010-06-09 23:09:06 +0400143
144 at91_set_gpio_output(AT91_PIN_PD1, 0);
145 at91_set_gpio_output(AT91_PIN_PD3, 0);
146}
147#endif
148
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200149#ifdef CONFIG_LCD
150
151vidinfo_t panel_info = {
Jeroen Hofsteee887b722014-06-10 00:16:23 +0200152 .vl_col = 480,
153 .vl_row = 272,
154 .vl_clk = 9000000,
155 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
156 ATMEL_LCDC_INVFRAME_NORMAL,
157 .vl_bpix = 3,
158 .vl_tft = 1,
159 .vl_hsync_len = 45,
160 .vl_left_margin = 1,
161 .vl_right_margin = 1,
162 .vl_vsync_len = 1,
163 .vl_upper_margin = 40,
164 .vl_lower_margin = 1,
165 .mmio = ATMEL_BASE_LCDC,
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200166};
167
168
169void lcd_enable(void)
170{
171 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
172}
173
174void lcd_disable(void)
175{
176 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
177}
178
179static void at91sam9m10g45ek_lcd_hw_init(void)
180{
181 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
182 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
183 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
184 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
185 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
186
187 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
188 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
189 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
190 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
191 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
192 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
193 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
194 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
195 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
196 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
197 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
198 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
199 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
200 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
201 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
202 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
203 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
204 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
205 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
206 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
207 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
208 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
209 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
210 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
211
Wenyou Yang78f89762016-02-03 10:16:50 +0800212 at91_periph_clk_enable(ATMEL_ID_LCDC);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200213
214 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
215}
216
217#ifdef CONFIG_LCD_INFO
218#include <nand.h>
219#include <version.h>
220
221void lcd_show_board_info(void)
222{
223 ulong dram_size, nand_size;
224 int i;
225 char temp[32];
226
227 lcd_printf ("%s\n", U_BOOT_VERSION);
228 lcd_printf ("(C) 2008 ATMEL Corp\n");
229 lcd_printf ("at91support@atmel.com\n");
230 lcd_printf ("%s CPU at %s MHz\n",
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000231 ATMEL_CPU_NAME,
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200232 strmhz(temp, get_cpu_clk_rate()));
233
234 dram_size = 0;
235 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
236 dram_size += gd->bd->bi_dram[i].size;
237 nand_size = 0;
238 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
Grygorii Strashko1e096a22017-06-26 19:13:03 -0500239 nand_size += get_nand_dev_by_index(i)->size;
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200240 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
241 dram_size >> 20,
242 nand_size >> 20 );
243}
244#endif /* CONFIG_LCD_INFO */
245#endif
246
Wenyou Yangcf6667c2017-04-18 15:15:50 +0800247#ifdef CONFIG_DEBUG_UART_BOARD_INIT
248void board_debug_uart_init(void)
249{
250 at91_seriald_hw_init();
251}
252#endif
253
254#ifdef CONFIG_BOARD_EARLY_INIT_F
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000255int board_early_init_f(void)
256{
Wenyou Yangcf6667c2017-04-18 15:15:50 +0800257#ifdef CONFIG_DEBUG_UART
258 debug_uart_init();
259#endif
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000260 return 0;
261}
Wenyou Yangcf6667c2017-04-18 15:15:50 +0800262#endif
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000263
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200264int board_init(void)
265{
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200266 /* arch number of AT91SAM9M10G45EK-Board */
267#ifdef CONFIG_AT91SAM9M10G45EK
268 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
269#elif defined CONFIG_AT91SAM9G45EKES
270 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
271#endif
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000272
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200273 /* adress of boot parameters */
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000274 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200275
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200276#ifdef CONFIG_CMD_NAND
277 at91sam9m10g45ek_nand_hw_init();
278#endif
Sergey Matyukevichd25010d2010-06-09 23:09:06 +0400279#ifdef CONFIG_CMD_USB
280 at91sam9m10g45ek_usb_hw_init();
281#endif
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200282#ifdef CONFIG_LCD
283 at91sam9m10g45ek_lcd_hw_init();
284#endif
285 return 0;
286}
287
288int dram_init(void)
289{
Thomas Petazzonia5e85762011-08-04 11:08:50 +0000290 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
291 CONFIG_SYS_SDRAM_SIZE);
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200292 return 0;
293}
294
295#ifdef CONFIG_RESET_PHY_R
296void reset_phy(void)
297{
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200298}
299#endif