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git01.mediatek.com / filogic / uboot / 4e8dbe2051e2bc9b152bf46b7b376f47b47a371e / . / arch / arm / dts / stm32mp157c.dtsi
blob: 50978efc7c22ae77ba4e3f29f6a953fe41e2920d [file] [log] [blame]
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
23
24 cpu1: cpu@1 {
25 compatible = "arm,cortex-a7";
26 device_type = "cpu";
27 reg = <1>;
28 };
29 };
30
31 psci {
32 compatible = "arm,psci";
33 method = "smc";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
36 };
37
38 aliases {
39 gpio0 = &gpioa;
40 gpio1 = &gpiob;
41 gpio2 = &gpioc;
42 gpio3 = &gpiod;
43 gpio4 = &gpioe;
44 gpio5 = &gpiof;
45 gpio6 = &gpiog;
46 gpio7 = &gpioh;
47 gpio8 = &gpioi;
48 gpio9 = &gpioj;
49 gpio10 = &gpiok;
50 serial0 = &usart1;
51 serial1 = &usart2;
52 serial2 = &usart3;
53 serial3 = &uart4;
54 serial4 = &uart5;
55 serial5 = &usart6;
56 serial6 = &uart7;
57 serial7 = &uart8;
58 };
59
60 intc: interrupt-controller@a0021000 {
61 compatible = "arm,cortex-a7-gic";
62 #interrupt-cells = <3>;
63 interrupt-controller;
64 reg = <0xa0021000 0x1000>,
65 <0xa0022000 0x2000>;
66 };
67
68 timer {
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 interrupt-parent = <&intc>;
75 };
76
77 clocks {
78 clk_hse: clk-hse {
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-frequency = <24000000>;
82 };
83
84 clk_hsi: clk-hsi {
85 #clock-cells = <0>;
86 compatible = "fixed-clock";
87 clock-frequency = <64000000>;
88 };
89
90 clk_lse: clk-lse {
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <32768>;
94 };
95
96 clk_lsi: clk-lsi {
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <32000>;
100 };
101
102 clk_csi: clk-csi {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 clock-frequency = <4000000>;
106 };
107 };
108
Patrice Chotard18cb6f52018-08-10 17:12:11 +0200[diff] [blame]109 pm_domain {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "st,stm32mp157c-pd";
113
114 pd_core_ret: core-ret-power-domain@1 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 reg = <1>;
118 #power-domain-cells = <0>;
119 label = "CORE-RETENTION";
120
121 pd_core: core-power-domain@2 {
122 reg = <2>;
123 #power-domain-cells = <0>;
124 label = "CORE";
125 };
126 };
127 };
128
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]129 soc {
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
133 interrupt-parent = <&intc>;
134 ranges;
135
136 timers2: timer@40000000 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 compatible = "st,stm32-timers";
140 reg = <0x40000000 0x400>;
141 clocks = <&rcc TIM2_K>;
142 clock-names = "int";
143 status = "disabled";
144
145 pwm {
146 compatible = "st,stm32-pwm";
147 status = "disabled";
148 };
149
150 timer@1 {
151 compatible = "st,stm32h7-timer-trigger";
152 reg = <1>;
153 status = "disabled";
154 };
155 };
156
157 timers3: timer@40001000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "st,stm32-timers";
161 reg = <0x40001000 0x400>;
162 clocks = <&rcc TIM3_K>;
163 clock-names = "int";
164 status = "disabled";
165
166 pwm {
167 compatible = "st,stm32-pwm";
168 status = "disabled";
169 };
170
171 timer@2 {
172 compatible = "st,stm32h7-timer-trigger";
173 reg = <2>;
174 status = "disabled";
175 };
176 };
177
178 timers4: timer@40002000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "st,stm32-timers";
182 reg = <0x40002000 0x400>;
183 clocks = <&rcc TIM4_K>;
184 clock-names = "int";
185 status = "disabled";
186
187 pwm {
188 compatible = "st,stm32-pwm";
189 status = "disabled";
190 };
191
192 timer@3 {
193 compatible = "st,stm32h7-timer-trigger";
194 reg = <3>;
195 status = "disabled";
196 };
197 };
198
199 timers5: timer@40003000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "st,stm32-timers";
203 reg = <0x40003000 0x400>;
204 clocks = <&rcc TIM5_K>;
205 clock-names = "int";
206 status = "disabled";
207
208 pwm {
209 compatible = "st,stm32-pwm";
210 status = "disabled";
211 };
212
213 timer@4 {
214 compatible = "st,stm32h7-timer-trigger";
215 reg = <4>;
216 status = "disabled";
217 };
218 };
219
220 timers6: timer@40004000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "st,stm32-timers";
224 reg = <0x40004000 0x400>;
225 clocks = <&rcc TIM6_K>;
226 clock-names = "int";
227 status = "disabled";
228
229 timer@5 {
230 compatible = "st,stm32h7-timer-trigger";
231 reg = <5>;
232 status = "disabled";
233 };
234 };
235
236 timers7: timer@40005000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "st,stm32-timers";
240 reg = <0x40005000 0x400>;
241 clocks = <&rcc TIM7_K>;
242 clock-names = "int";
243 status = "disabled";
244
245 timer@6 {
246 compatible = "st,stm32h7-timer-trigger";
247 reg = <6>;
248 status = "disabled";
249 };
250 };
251
252 timers12: timer@40006000 {
253 #address-cells = <1>;
254 #size-cells = <0>;
255 compatible = "st,stm32-timers";
256 reg = <0x40006000 0x400>;
257 clocks = <&rcc TIM12_K>;
258 clock-names = "int";
259 status = "disabled";
260
261 pwm {
262 compatible = "st,stm32-pwm";
263 status = "disabled";
264 };
265
266 timer@11 {
267 compatible = "st,stm32h7-timer-trigger";
268 reg = <11>;
269 status = "disabled";
270 };
271 };
272
273 timers13: timer@40007000 {
274 #address-cells = <1>;
275 #size-cells = <0>;
276 compatible = "st,stm32-timers";
277 reg = <0x40007000 0x400>;
278 clocks = <&rcc TIM13_K>;
279 clock-names = "int";
280 status = "disabled";
281
282 pwm {
283 compatible = "st,stm32-pwm";
284 status = "disabled";
285 };
286
287 timer@12 {
288 compatible = "st,stm32h7-timer-trigger";
289 reg = <12>;
290 status = "disabled";
291 };
292 };
293
294 timers14: timer@40008000 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "st,stm32-timers";
298 reg = <0x40008000 0x400>;
299 clocks = <&rcc TIM14_K>;
300 clock-names = "int";
301 status = "disabled";
302
303 pwm {
304 compatible = "st,stm32-pwm";
305 status = "disabled";
306 };
307
308 timer@13 {
309 compatible = "st,stm32h7-timer-trigger";
310 reg = <13>;
311 status = "disabled";
312 };
313 };
314
315 lptimer1: timer@40009000 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "st,stm32-lptimer";
319 reg = <0x40009000 0x400>;
320 clocks = <&rcc LPTIM1_K>;
321 clock-names = "mux";
322 status = "disabled";
323
324 pwm {
325 compatible = "st,stm32-pwm-lp";
326 #pwm-cells = <3>;
327 status = "disabled";
328 };
329
330 trigger@0 {
331 compatible = "st,stm32-lptimer-trigger";
332 reg = <0>;
333 status = "disabled";
334 };
335
336 counter {
337 compatible = "st,stm32-lptimer-counter";
338 status = "disabled";
339 };
340 };
341
342 usart2: serial@4000e000 {
343 compatible = "st,stm32h7-uart";
344 reg = <0x4000e000 0x400>;
345 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&rcc USART2_K>;
347 status = "disabled";
348 };
349
350 usart3: serial@4000f000 {
351 compatible = "st,stm32h7-uart";
352 reg = <0x4000f000 0x400>;
353 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&rcc USART3_K>;
355 status = "disabled";
356 };
357
358 uart4: serial@40010000 {
359 compatible = "st,stm32h7-uart";
360 reg = <0x40010000 0x400>;
361 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&rcc UART4_K>;
363 status = "disabled";
364 };
365
366 uart5: serial@40011000 {
367 compatible = "st,stm32h7-uart";
368 reg = <0x40011000 0x400>;
369 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&rcc UART5_K>;
371 status = "disabled";
372 };
373
374 i2c1: i2c@40012000 {
375 compatible = "st,stm32f7-i2c";
376 reg = <0x40012000 0x400>;
377 interrupt-names = "event", "error";
378 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&rcc I2C1_K>;
381 resets = <&rcc I2C1_R>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 status = "disabled";
385 };
386
387 i2c2: i2c@40013000 {
388 compatible = "st,stm32f7-i2c";
389 reg = <0x40013000 0x400>;
390 interrupt-names = "event", "error";
391 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&rcc I2C2_K>;
394 resets = <&rcc I2C2_R>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397 status = "disabled";
398 };
399
400 i2c3: i2c@40014000 {
401 compatible = "st,stm32f7-i2c";
402 reg = <0x40014000 0x400>;
403 interrupt-names = "event", "error";
404 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&rcc I2C3_K>;
407 resets = <&rcc I2C3_R>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 status = "disabled";
411 };
412
413 i2c5: i2c@40015000 {
414 compatible = "st,stm32f7-i2c";
415 reg = <0x40015000 0x400>;
416 interrupt-names = "event", "error";
417 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&rcc I2C5_K>;
420 resets = <&rcc I2C5_R>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 status = "disabled";
424 };
425
426 cec: cec@40016000 {
427 compatible = "st,stm32-cec";
428 reg = <0x40016000 0x400>;
429 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&rcc CEC_K>, <&clk_lse>;
431 clock-names = "cec", "hdmi-cec";
432 status = "disabled";
433 };
434
435 dac: dac@40017000 {
436 compatible = "st,stm32h7-dac-core";
437 reg = <0x40017000 0x400>;
438 clocks = <&rcc DAC12>;
439 clock-names = "pclk";
440 #address-cells = <1>;
441 #size-cells = <0>;
442 status = "disabled";
443
444 dac1: dac@1 {
445 compatible = "st,stm32-dac";
446 #io-channels-cells = <1>;
447 reg = <1>;
448 status = "disabled";
449 };
450
451 dac2: dac@2 {
452 compatible = "st,stm32-dac";
453 #io-channels-cells = <1>;
454 reg = <2>;
455 status = "disabled";
456 };
457 };
458
459 uart7: serial@40018000 {
460 compatible = "st,stm32h7-uart";
461 reg = <0x40018000 0x400>;
462 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&rcc UART7_K>;
464 status = "disabled";
465 };
466
467 uart8: serial@40019000 {
468 compatible = "st,stm32h7-uart";
469 reg = <0x40019000 0x400>;
470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&rcc UART8_K>;
472 status = "disabled";
473 };
474
475 timers1: timer@44000000 {
476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "st,stm32-timers";
479 reg = <0x44000000 0x400>;
480 clocks = <&rcc TIM1_K>;
481 clock-names = "int";
482 status = "disabled";
483
484 pwm {
485 compatible = "st,stm32-pwm";
486 status = "disabled";
487 };
488
489 timer@0 {
490 compatible = "st,stm32h7-timer-trigger";
491 reg = <0>;
492 status = "disabled";
493 };
494 };
495
496 timers8: timer@44001000 {
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "st,stm32-timers";
500 reg = <0x44001000 0x400>;
501 clocks = <&rcc TIM8_K>;
502 clock-names = "int";
503 status = "disabled";
504
505 pwm {
506 compatible = "st,stm32-pwm";
507 status = "disabled";
508 };
509
510 timer@7 {
511 compatible = "st,stm32h7-timer-trigger";
512 reg = <7>;
513 status = "disabled";
514 };
515 };
516
517 usart6: serial@44003000 {
518 compatible = "st,stm32h7-uart";
519 reg = <0x44003000 0x400>;
520 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&rcc USART6_K>;
522 status = "disabled";
523 };
524
525 timers15: timer@44006000 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "st,stm32-timers";
529 reg = <0x44006000 0x400>;
530 clocks = <&rcc TIM15_K>;
531 clock-names = "int";
532 status = "disabled";
533
534 pwm {
535 compatible = "st,stm32-pwm";
536 status = "disabled";
537 };
538
539 timer@14 {
540 compatible = "st,stm32h7-timer-trigger";
541 reg = <14>;
542 status = "disabled";
543 };
544 };
545
546 timers16: timer@44007000 {
547 #address-cells = <1>;
548 #size-cells = <0>;
549 compatible = "st,stm32-timers";
550 reg = <0x44007000 0x400>;
551 clocks = <&rcc TIM16_K>;
552 clock-names = "int";
553 status = "disabled";
554
555 pwm {
556 compatible = "st,stm32-pwm";
557 status = "disabled";
558 };
559 timer@15 {
560 compatible = "st,stm32h7-timer-trigger";
561 reg = <15>;
562 status = "disabled";
563 };
564 };
565
566 timers17: timer@44008000 {
567 #address-cells = <1>;
568 #size-cells = <0>;
569 compatible = "st,stm32-timers";
570 reg = <0x44008000 0x400>;
571 clocks = <&rcc TIM17_K>;
572 clock-names = "int";
573 status = "disabled";
574
575 pwm {
576 compatible = "st,stm32-pwm";
577 status = "disabled";
578 };
579
580 timer@16 {
581 compatible = "st,stm32h7-timer-trigger";
582 reg = <16>;
583 status = "disabled";
584 };
585 };
586
587 dma1: dma@48000000 {
588 compatible = "st,stm32-dma";
589 reg = <0x48000000 0x400>;
590 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&rcc DMA1>;
599 #dma-cells = <4>;
600 st,mem2mem;
601 dma-requests = <8>;
602 };
603
604 dma2: dma@48001000 {
605 compatible = "st,stm32-dma";
606 reg = <0x48001000 0x400>;
607 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&rcc DMA2>;
616 #dma-cells = <4>;
617 st,mem2mem;
618 dma-requests = <8>;
619 };
620
621 dmamux1: dma-router@48002000 {
622 compatible = "st,stm32h7-dmamux";
623 reg = <0x48002000 0x1c>;
624 #dma-cells = <3>;
625 dma-requests = <128>;
626 dma-masters = <&dma1 &dma2>;
627 dma-channels = <16>;
628 clocks = <&rcc DMAMUX>;
629 };
630
Patrice Chotardb5c87a42018-08-06 09:54:04 +0200[diff] [blame]631 adc: adc@48003000 {
632 compatible = "st,stm32mp1-adc-core";
633 reg = <0x48003000 0x400>;
634 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
637 clock-names = "bus", "adc";
638 interrupt-controller;
639 #interrupt-cells = <1>;
640 #address-cells = <1>;
641 #size-cells = <0>;
642 status = "disabled";
643
644 adc1: adc@0 {
645 compatible = "st,stm32mp1-adc";
646 #io-channel-cells = <1>;
647 reg = <0x0>;
648 interrupt-parent = <&adc>;
649 interrupts = <0>;
650 status = "disabled";
651 };
652
653 adc2: adc@100 {
654 compatible = "st,stm32mp1-adc";
655 #io-channel-cells = <1>;
656 reg = <0x100>;
657 interrupt-parent = <&adc>;
658 interrupts = <1>;
659 status = "disabled";
660 };
661 };
662
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]663 sdmmc3: sdmmc@48004000 {
664 compatible = "st,stm32-sdmmc2";
665 reg = <0x48004000 0x400>, <0x48005000 0x400>;
666 reg-names = "sdmmc", "delay";
667 interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
668 clocks = <&rcc SDMMC3_K>;
669 resets = <&rcc SDMMC3_R>;
670 st,idma = <1>;
671 cap-sd-highspeed;
672 cap-mmc-highspeed;
673 max-frequency = <120000000>;
674 status = "disabled";
675 };
676
Patrice Chotard18cb6f52018-08-10 17:12:11 +0200[diff] [blame]677 usbotg_hs: usb-otg@49000000 {
678 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
679 reg = <0x49000000 0x10000>;
680 clocks = <&rcc USBO_K>;
681 clock-names = "otg";
682 resets = <&rcc USBO_R>;
683 reset-names = "dwc2";
684 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
685 g-rx-fifo-size = <256>;
686 g-np-tx-fifo-size = <32>;
687 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
688 dr_mode = "otg";
689 power-domains = <&pd_core>;
690 status = "disabled";
691 };
692
Benjamin Gaignard77611122018-11-27 13:49:52 +0100[diff] [blame]693 hwspinlock: hwspinlock@4c000000 {
694 compatible = "st,stm32-hwspinlock";
695 #hwlock-cells = <1>;
696 reg = <0x4c000000 0x400>;
697 clocks = <&rcc HSEM>;
698 clock-names = "hwspinlock";
699 status = "disabled";
700 };
701
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]702 rcc: rcc@50000000 {
703 compatible = "st,stm32mp1-rcc", "syscon";
704 reg = <0x50000000 0x1000>;
705 #clock-cells = <1>;
706 #reset-cells = <1>;
707 };
708
709 rcc_reboot: rcc-reboot@50000000 {
710 compatible = "syscon-reboot";
711 regmap = <&rcc>;
712 offset = <0x404>;
713 mask = <0x1>;
714 };
715
716 pwr: pwr@50001000 {
717 compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
718 reg = <0x50001000 0x400>;
719 system-power-controller;
720 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
721 st,sysrcc = <&rcc>;
722 clocks = <&rcc PLL2_R>;
723 clock-names = "phyclk";
724
725 pwr-regulators@c {
726 compatible = "st,stm32mp1,pwr-reg";
727 st,tzcr = <&rcc 0x0 0x1>;
728
729 reg11: reg11 {
730 regulator-name = "reg11";
731 regulator-min-microvolt = <1100000>;
732 regulator-max-microvolt = <1100000>;
733 };
734
735 reg18: reg18 {
736 regulator-name = "reg18";
737 regulator-min-microvolt = <1800000>;
738 regulator-max-microvolt = <1800000>;
739 };
740
741 usb33: usb33 {
742 regulator-name = "usb33";
743 regulator-min-microvolt = <3300000>;
744 regulator-max-microvolt = <3300000>;
745 };
746 };
747 };
748
749 exti: interrupt-controller@5000d000 {
750 compatible = "st,stm32mp1-exti", "syscon";
751 interrupt-controller;
752 #interrupt-cells = <2>;
753 reg = <0x5000d000 0x400>;
754 };
755
756 syscfg: system-config@50020000 {
Patrick Delaunay63ae49e2019-02-27 17:01:23 +0100[diff] [blame]757 compatible = "st,stm32mp157-syscfg", "syscon";
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]758 reg = <0x50020000 0x400>;
759 };
760
761 lptimer2: timer@50021000 {
762 #address-cells = <1>;
763 #size-cells = <0>;
764 compatible = "st,stm32-lptimer";
765 reg = <0x50021000 0x400>;
766 clocks = <&rcc LPTIM2_K>;
767 clock-names = "mux";
768 status = "disabled";
769
770 pwm {
771 compatible = "st,stm32-pwm-lp";
772 #pwm-cells = <3>;
773 status = "disabled";
774 };
775
776 trigger@1 {
777 compatible = "st,stm32-lptimer-trigger";
778 reg = <1>;
779 status = "disabled";
780 };
781
782 counter {
783 compatible = "st,stm32-lptimer-counter";
784 status = "disabled";
785 };
786 };
787
788 lptimer3: timer@50022000 {
789 #address-cells = <1>;
790 #size-cells = <0>;
791 compatible = "st,stm32-lptimer";
792 reg = <0x50022000 0x400>;
793 clocks = <&rcc LPTIM3_K>;
794 clock-names = "mux";
795 status = "disabled";
796
797 pwm {
798 compatible = "st,stm32-pwm-lp";
799 #pwm-cells = <3>;
800 status = "disabled";
801 };
802
803 trigger@2 {
804 compatible = "st,stm32-lptimer-trigger";
805 reg = <2>;
806 status = "disabled";
807 };
808 };
809
810 lptimer4: timer@50023000 {
811 compatible = "st,stm32-lptimer";
812 reg = <0x50023000 0x400>;
813 clocks = <&rcc LPTIM4_K>;
814 clock-names = "mux";
815 status = "disabled";
816
817 pwm {
818 compatible = "st,stm32-pwm-lp";
819 #pwm-cells = <3>;
820 status = "disabled";
821 };
822 };
823
824 lptimer5: timer@50024000 {
825 compatible = "st,stm32-lptimer";
826 reg = <0x50024000 0x400>;
827 clocks = <&rcc LPTIM5_K>;
828 clock-names = "mux";
829 status = "disabled";
830
831 pwm {
832 compatible = "st,stm32-pwm-lp";
833 #pwm-cells = <3>;
834 status = "disabled";
835 };
836 };
837
838 vrefbuf: vrefbuf@50025000 {
839 compatible = "st,stm32-vrefbuf";
840 reg = <0x50025000 0x8>;
841 regulator-min-microvolt = <1500000>;
842 regulator-max-microvolt = <2500000>;
843 clocks = <&rcc VREF>;
844 status = "disabled";
845 };
846
847 cryp1: cryp@54001000 {
848 compatible = "st,stm32mp1-cryp";
849 reg = <0x54001000 0x400>;
850 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&rcc CRYP1>;
852 resets = <&rcc CRYP1_R>;
853 status = "disabled";
854 };
855
856 rng1: rng@54003000 {
857 compatible = "st,stm32-rng";
858 reg = <0x54003000 0x400>;
859 clocks = <&rcc RNG1_K>;
860 resets = <&rcc RNG1_R>;
861 status = "disabled";
862 };
863
864 mdma1: dma@58000000 {
865 compatible = "st,stm32h7-mdma";
866 reg = <0x58000000 0x1000>;
867 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&rcc MDMA>;
869 #dma-cells = <5>;
870 dma-channels = <32>;
871 dma-requests = <48>;
872 };
873
874 qspi: qspi@58003000 {
875 compatible = "st,stm32f469-qspi";
876 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
877 reg-names = "qspi", "qspi_mm";
878 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&rcc QSPI_K>;
880 resets = <&rcc QSPI_R>;
881 status = "disabled";
882 };
883
884 sdmmc1: sdmmc@58005000 {
885 compatible = "st,stm32-sdmmc2";
886 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
887 reg-names = "sdmmc", "delay";
888 clocks = <&rcc SDMMC1_K>;
889 resets = <&rcc SDMMC1_R>;
890 st,idma = <1>;
891 cap-sd-highspeed;
892 cap-mmc-highspeed;
893 max-frequency = <120000000>;
894 status = "disabled";
895 };
896
897 sdmmc2: sdmmc@58007000 {
898 compatible = "st,stm32-sdmmc2";
899 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
900 reg-names = "sdmmc", "delay";
901 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
902 clocks = <&rcc SDMMC2_K>;
903 resets = <&rcc SDMMC2_R>;
904 st,idma = <1>;
905 cap-sd-highspeed;
906 cap-mmc-highspeed;
907 max-frequency = <120000000>;
908 status = "disabled";
909 };
910
911 crc1: crc@58009000 {
912 compatible = "st,stm32f7-crc";
913 reg = <0x58009000 0x400>;
914 clocks = <&rcc CRC1>;
915 status = "disabled";
916 };
917
918 usbh_ohci: usbh-ohci@5800c000 {
919 compatible = "generic-ohci";
920 reg = <0x5800c000 0x1000>;
921 clocks = <&rcc USBH>;
922 resets = <&rcc USBH_R>;
923 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
924 status = "disabled";
925 };
926
927 usbh_ehci: usbh-ehci@5800d000 {
928 compatible = "generic-ehci";
929 reg = <0x5800d000 0x1000>;
930 clocks = <&rcc USBH>;
931 resets = <&rcc USBH_R>;
932 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
933 companion = <&usbh_ohci>;
934 status = "disabled";
935 };
936
937 dsi: dsi@5a000000 {
938 compatible = "st,stm32-dsi";
939 reg = <0x5a000000 0x800>;
940 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
941 clock-names = "pclk", "ref", "px_clk";
942 resets = <&rcc DSI_R>;
943 reset-names = "apb";
944 status = "disabled";
945 };
946
947 ltdc: display-controller@5a001000 {
948 compatible = "st,stm32-ltdc";
949 reg = <0x5a001000 0x400>;
950 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&rcc LTDC_PX>;
953 clock-names = "lcd";
954 resets = <&rcc LTDC_R>;
955 status = "disabled";
956 };
957
958 usbphyc: usbphyc@5a006000 {
959 #address-cells = <1>;
960 #size-cells = <0>;
961 compatible = "st,stm32mp1-usbphyc";
962 reg = <0x5a006000 0x1000>;
963 clocks = <&rcc USBPHY_K>;
964 resets = <&rcc USBPHY_R>;
965 status = "disabled";
966
967 usbphyc_port0: usb-phy@0 {
968 #phy-cells = <0>;
969 reg = <0>;
970 };
971
972 usbphyc_port1: usb-phy@1 {
973 #phy-cells = <1>;
974 reg = <1>;
975 };
976 };
977
978 usart1: serial@5c000000 {
979 compatible = "st,stm32h7-uart";
980 reg = <0x5c000000 0x400>;
981 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&rcc USART1_K>;
983 status = "disabled";
984 };
985
986 i2c4: i2c@5c002000 {
987 compatible = "st,stm32f7-i2c";
988 reg = <0x5c002000 0x400>;
989 interrupt-names = "event", "error";
990 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&rcc I2C4_K>;
993 resets = <&rcc I2C4_R>;
994 #address-cells = <1>;
995 #size-cells = <0>;
996 status = "disabled";
997 };
998
Patrick Delaunaybdd71362019-02-27 17:01:27 +0100[diff] [blame]999 bsec: nvmem@5c005000 {
1000 compatible = "st,stm32mp15-bsec";
1001 reg = <0x5c005000 0x400>;
1002 #address-cells = <1>;
1003 #size-cells = <1>;
1004 };
1005
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]1006 i2c6: i2c@5c009000 {
1007 compatible = "st,stm32f7-i2c";
1008 reg = <0x5c009000 0x400>;
1009 interrupt-names = "event", "error";
1010 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1011 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&rcc I2C6_K>;
1013 resets = <&rcc I2C6_R>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 status = "disabled";
1017 };
1018 };
1019};