Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2018 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef __IMX8M_CM_H |
| 7 | #define __IMX8M_CM_H |
| 8 | |
| 9 | #include <linux/sizes.h> |
| 10 | #include <linux/stringify.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | |
Simon Glass | 209ae76 | 2024-09-29 19:49:49 -0600 | [diff] [blame] | 13 | #ifdef CONFIG_XPL_BUILD |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 14 | |
| 15 | /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ |
Tom Rini | fb52b94 | 2022-12-04 10:04:49 -0500 | [diff] [blame] | 16 | #define CFG_MALLOC_F_ADDR 0x182000 |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 17 | /* For RAW image gives a error info not panic */ |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 18 | |
| 19 | #endif |
| 20 | |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 21 | /* ENET Config */ |
| 22 | /* ENET1 */ |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 23 | |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 24 | #define BOOT_TARGET_DEVICES(func) \ |
| 25 | func(MMC, mmc, 0) \ |
| 26 | func(MMC, mmc, 1) \ |
| 27 | func(DHCP, dhcp, na) |
| 28 | |
| 29 | #include <config_distro_bootcmd.h> |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 30 | |
| 31 | /* Initial environment variables */ |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 32 | #define CFG_EXTRA_ENV_SETTINGS \ |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 33 | BOOTENV \ |
| 34 | "scriptaddr=0x43500000\0" \ |
| 35 | "kernel_addr_r=0x40880000\0" \ |
| 36 | "image=Image\0" \ |
| 37 | "console=ttymxc0,115200\0" \ |
| 38 | "fdt_addr=0x43000000\0" \ |
| 39 | "boot_fdt=try\0" \ |
| 40 | "fdt_file=imx8mq-cm.dtb\0" \ |
| 41 | "initrd_addr=0x43800000\0" \ |
| 42 | "bootm_size=0x10000000\0" \ |
Tom Rini | b113bca | 2021-12-11 14:55:52 -0500 | [diff] [blame] | 43 | "mmcpart=1\0" \ |
Peng Fan | bb4bb58 | 2022-04-15 12:23:41 +0800 | [diff] [blame] | 44 | "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 45 | |
| 46 | /* Link Definitions */ |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 47 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 48 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 49 | #define CFG_SYS_INIT_RAM_SIZE 0x80000 |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 50 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 51 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 52 | #define PHYS_SDRAM 0x40000000 |
| 53 | #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ |
| 54 | |
Tom Rini | a17aa19 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 55 | #define CFG_MXC_UART_BASE UART_BASE_ADDR(1) |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 56 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 57 | #define CFG_SYS_FSL_USDHC_NUM 2 |
| 58 | #define CFG_SYS_FSL_ESDHC_ADDR 0 |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 59 | |
Ilko Iliev | 2b4ed30 | 2021-04-23 09:45:52 +0200 | [diff] [blame] | 60 | #endif |