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Ilko Iliev2b4ed302021-04-23 09:45:52 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2018 NXP
4 */
5
6#ifndef __IMX8M_CM_H
7#define __IMX8M_CM_H
8
9#include <linux/sizes.h>
10#include <linux/stringify.h>
11#include <asm/arch/imx-regs.h>
12
Simon Glass209ae762024-09-29 19:49:49 -060013#ifdef CONFIG_XPL_BUILD
Ilko Iliev2b4ed302021-04-23 09:45:52 +020014
15/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
Tom Rinifb52b942022-12-04 10:04:49 -050016#define CFG_MALLOC_F_ADDR 0x182000
Ilko Iliev2b4ed302021-04-23 09:45:52 +020017/* For RAW image gives a error info not panic */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020018
19#endif
20
Ilko Iliev2b4ed302021-04-23 09:45:52 +020021/* ENET Config */
22/* ENET1 */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020023
Ilko Iliev2b4ed302021-04-23 09:45:52 +020024#define BOOT_TARGET_DEVICES(func) \
25 func(MMC, mmc, 0) \
26 func(MMC, mmc, 1) \
27 func(DHCP, dhcp, na)
28
29#include <config_distro_bootcmd.h>
Ilko Iliev2b4ed302021-04-23 09:45:52 +020030
31/* Initial environment variables */
Tom Rinic9edebe2022-12-04 10:03:50 -050032#define CFG_EXTRA_ENV_SETTINGS \
Ilko Iliev2b4ed302021-04-23 09:45:52 +020033 BOOTENV \
34 "scriptaddr=0x43500000\0" \
35 "kernel_addr_r=0x40880000\0" \
36 "image=Image\0" \
37 "console=ttymxc0,115200\0" \
38 "fdt_addr=0x43000000\0" \
39 "boot_fdt=try\0" \
40 "fdt_file=imx8mq-cm.dtb\0" \
41 "initrd_addr=0x43800000\0" \
42 "bootm_size=0x10000000\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050043 "mmcpart=1\0" \
Peng Fanbb4bb582022-04-15 12:23:41 +080044 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
Ilko Iliev2b4ed302021-04-23 09:45:52 +020045
46/* Link Definitions */
Ilko Iliev2b4ed302021-04-23 09:45:52 +020047
Tom Rini6a5dccc2022-11-16 13:10:41 -050048#define CFG_SYS_INIT_RAM_ADDR 0x40000000
49#define CFG_SYS_INIT_RAM_SIZE 0x80000
Ilko Iliev2b4ed302021-04-23 09:45:52 +020050
Tom Rinibb4dd962022-11-16 13:10:37 -050051#define CFG_SYS_SDRAM_BASE 0x40000000
Ilko Iliev2b4ed302021-04-23 09:45:52 +020052#define PHYS_SDRAM 0x40000000
53#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
54
Tom Rinia17aa192022-12-04 10:04:55 -050055#define CFG_MXC_UART_BASE UART_BASE_ADDR(1)
Ilko Iliev2b4ed302021-04-23 09:45:52 +020056
Tom Rini376b88a2022-10-28 20:27:13 -040057#define CFG_SYS_FSL_USDHC_NUM 2
58#define CFG_SYS_FSL_ESDHC_ADDR 0
Ilko Iliev2b4ed302021-04-23 09:45:52 +020059
Ilko Iliev2b4ed302021-04-23 09:45:52 +020060#endif