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git01.mediatek.com / filogic / uboot / 625bc3f8d808f74f8fbead519dde9aac39c5d719 / . / board / davinci / da8xxevm / u-boot-spl-da850evm.lds
blob: 56d6f4f114b9c6ea427c74d8809b0b30891b8104 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]2/*
3 * (C) Copyright 2002
4 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
5 *
6 * (C) Copyright 2008
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]8 */
9
Tom Rini2aaa27d2019-01-22 17:09:26 -0500[diff] [blame]10MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
Albert ARIBAUDa02e3cc2013-04-12 05:14:32 +0000[diff] [blame]11 LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]12
Adam Ford1264bdf2019-02-25 21:53:46 -0600[diff] [blame]13MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]14 LENGTH = 0x1080000 }
Adam Ford1264bdf2019-02-25 21:53:46 -0600[diff] [blame]15
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]16OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
17OUTPUT_ARCH(arm)
18ENTRY(_start)
19SECTIONS
20{
21 . = 0x00000000;
22
23 . = ALIGN(4);
24 .text :
25 {
26 __start = .;
Benoît Thébaudeau3f7740f2014-08-21 15:43:11 +0200[diff] [blame]27 *(.vectors)
Benoît Thébaudeau3954db82013-04-11 09:36:03 +0000[diff] [blame]28 arch/arm/cpu/arm926ejs/start.o (.text*)
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]29 *(.text*)
30 } >.sram
31
32 . = ALIGN(4);
33 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
34
35 . = ALIGN(4);
36 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]37
38 . = ALIGN(4);
Andrew Scull5a9095c2022-05-30 10:00:04 +0000[diff] [blame]39 __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); } >.sram
Fabien Parentd96020c2016-11-29 14:23:40 +0100[diff] [blame]40
41 . = ALIGN(4);
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]42 .rel.dyn : {
43 __rel_dyn_start = .;
44 *(.rel*)
45 __rel_dyn_end = .;
46 } >.sram
47
Adam Ford1264bdf2019-02-25 21:53:46 -0600[diff] [blame]48 __image_copy_end = .;
Ilias Apalodimas80808462024-05-28 09:18:27 +0300[diff] [blame]49 _end = .;
Adam Ford1264bdf2019-02-25 21:53:46 -0600[diff] [blame]50 _image_binary_end = .;
51
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]52 .bss :
53 {
54 . = ALIGN(4);
55 __bss_start = .;
56 *(.bss*)
57 . = ALIGN(4);
Simon Glassed70c8f2013-03-14 06:54:53 +0000[diff] [blame]58 __bss_end = .;
Adam Ford1264bdf2019-02-25 21:53:46 -0600[diff] [blame]59 } >.sdram
Christian Riesch63e341b2011-12-09 09:47:37 +0000[diff] [blame]60}