blob: a9cfc10d0c0a249b15a9c3a6f543ea914e1d58c6 [file] [log] [blame]
Dirk Eibach96580242009-07-17 14:16:40 +02001/*
2 * (C) Copyright 2009
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach96580242009-07-17 14:16:40 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibach96580242009-07-17 14:16:40 +020012#define CONFIG_DLVISION 1 /* on a Neo board */
13
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020014#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
Dirk Eibach96580242009-07-17 14:16:40 +020016/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME dlvision
Dirk Eibacha3162032013-06-26 16:04:31 +020020#define CONFIG_IDENT_STRING " dlvision 0.02"
Dirk Eibach96580242009-07-17 14:16:40 +020021#include "amcc-common.h"
22
23#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
24#define CONFIG_MISC_INIT_R /* call misc_init_r */
Dirk Eibachab81cc62014-07-25 10:10:24 +020025#define CONFIG_SYS_GENERIC_BOARD
Dirk Eibach96580242009-07-17 14:16:40 +020026
27#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
28
29/*
30 * Configure PLL
31 */
32#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
33#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
34
35/* new uImage format support */
36#define CONFIG_FIT
37#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
Dirk Eibach5f673f92014-11-13 19:21:12 +010038#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibach96580242009-07-17 14:16:40 +020039
40#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
41
42/*
43 * Default environment variables
44 */
45#define CONFIG_EXTRA_ENV_SETTINGS \
46 CONFIG_AMCC_DEF_ENV \
47 CONFIG_AMCC_DEF_ENV_POWERPC \
48 CONFIG_AMCC_DEF_ENV_NOR_UPD \
49 "kernel_addr=fc000000\0" \
50 "fdt_addr=fc1e0000\0" \
51 "ramdisk_addr=fc200000\0" \
52 ""
53
54#define CONFIG_PHY_ADDR 4 /* PHY address */
55#define CONFIG_HAS_ETH0
56#define CONFIG_HAS_ETH1
57#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
58#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
59
60/*
61 * Commands additional to the ones defined in amcc-common.h
62 */
Dirk Eibach5f673f92014-11-13 19:21:12 +010063#define CONFIG_CMD_DTT
64#undef CONFIG_CMD_DHCP
65#undef CONFIG_CMD_DIAG
Dirk Eibach96580242009-07-17 14:16:40 +020066#undef CONFIG_CMD_EEPROM
Dirk Eibach5f673f92014-11-13 19:21:12 +010067#undef CONFIG_CMD_ELF
68#undef CONFIG_CMD_I2C
69#undef CONFIG_CMD_IRQ
70#undef CONFIG_CMD_NFS
Dirk Eibach96580242009-07-17 14:16:40 +020071
72/*
73 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
74 */
75#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
76
77/* SDRAM timings used in datasheet */
78#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
79#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
80#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
81#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
82#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
83
84/*
85 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
86 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
87 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
88 * The Linux BASE_BAUD define should match this configuration.
89 * baseBaud = cpuClock/(uartDivisor*16)
90 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
91 * set Linux BASE_BAUD to 403200.
92 */
Stefan Roese3ddce572010-09-20 16:05:31 +020093#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Dirk Eibach96580242009-07-17 14:16:40 +020094#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
95#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
96#define CONFIG_SYS_BASE_BAUD 691200
97
98/*
99 * I2C stuff
100 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000101#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibach96580242009-07-17 14:16:40 +0200102
103/*
104 * FLASH organization
105 */
106#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
107#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
108
109#define CONFIG_SYS_FLASH_BASE 0xFC000000
110#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
111
112#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
113#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
114
115#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
116#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
117
118#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibach96580242009-07-17 14:16:40 +0200119
120#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
121#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
122
123#ifdef CONFIG_ENV_IS_IN_FLASH
124#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
125#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
126#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
127
128/* Address and size of Redundant Environment Sector */
129#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
130#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
131#endif
132
133/*
134 * PPC405 GPIO Configuration
135 */
136#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
137{ \
138/* GPIO Core 0 */ \
139{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
140{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
141{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
142{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
143{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
144{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
145{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
146{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
147{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
148{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
149{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
150{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
151{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
152{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
153{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
154{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
155{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
156{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
157{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
158{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
159{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
160{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
162{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
163{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
164{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
165{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
166{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
167{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
168{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
169{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
170{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
171} \
172}
173
174/*
175 * Definitions for initial stack pointer and data area (in data cache)
176 */
177/* use on chip memory (OCM) for temperary stack until sdram is tested */
178#define CONFIG_SYS_TEMP_STACK_OCM 1
179
180/* On Chip Memory location */
181#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
182#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
183#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200184#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
Dirk Eibach96580242009-07-17 14:16:40 +0200185
Dirk Eibach96580242009-07-17 14:16:40 +0200186#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200187 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibach96580242009-07-17 14:16:40 +0200188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
189
190/*
191 * External Bus Controller (EBC) Setup
192 */
193
194/* Memory Bank 0 (NOR-FLASH) initialization */
195#define CONFIG_SYS_EBC_PB0AP 0x92015480
196/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
197#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
198
199/* Memory Bank 1 (NVRAM) initializatio */
200#define CONFIG_SYS_EBC_PB1AP 0x92015480
201/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
202#define CONFIG_SYS_EBC_PB1CR 0xFB858000
203
204/* Memory Bank 2 (UART) initialization */
205#define CONFIG_UART_BASE 0x7f100000
206#define CONFIG_SYS_EBC_PB2AP 0x92015480
207/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
208#define CONFIG_SYS_EBC_PB2CR 0x7f118000
209
210/* Memory Bank 3 (Latches) initialization */
211#define CONFIG_SYS_LATCH_BASE 0x7f200000
212#define CONFIG_SYS_EBC_PB3AP 0x92015480
213/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
214#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
215
216#endif /* __CONFIG_H */