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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / dts / upstream / src / arm / nxp / imx / imx6qdl-tx6.dtsi
blob: 2fa37d1b16cc0473004f5a64969b0dc6112d3104 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/input/input.h>
44#include <dt-bindings/interrupt-controller/irq.h>
45#include <dt-bindings/pwm/pwm.h>
46#include <dt-bindings/sound/fsl-imx-audmux.h>
47
48/ {
49 aliases {
50 can0 = &can2;
51 can1 = &can1;
52 ethernet0 = &fec;
53 lcdif-23bit-pins-a = &pinctrl_disp0_1;
54 lcdif-24bit-pins-a = &pinctrl_disp0_2;
55 pwm0 = &pwm1;
56 pwm1 = &pwm2;
57 reg-can-xcvr = &reg_can_xcvr;
58 stk5led = &user_led;
59 usbotg = &usbotg;
60 sdhc0 = &usdhc1;
61 sdhc1 = &usdhc2;
62 };
63
64 memory@10000000 {
65 device_type = "memory";
66 reg = <0x10000000 0>; /* will be filled by U-Boot */
67 };
68
69 clocks {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
Tom Rini844493d2025-01-26 16:17:47 -0600[diff] [blame]73 mclk: clock {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]74 compatible = "fixed-clock";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]75 #clock-cells = <0>;
76 clock-frequency = <26000000>;
77 };
78 };
79
80 gpio-keys {
81 compatible = "gpio-keys";
82
83 power {
84 label = "Power Button";
85 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
86 linux,code = <KEY_POWER>;
87 wakeup-source;
88 };
89 };
90
91 leds {
92 compatible = "gpio-leds";
93
94 user_led: led-user {
95 label = "Heartbeat";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_user_led>;
98 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
99 linux,default-trigger = "heartbeat";
100 };
101 };
102
103 reg_3v3_etn: regulator-3v3-etn {
104 compatible = "regulator-fixed";
105 regulator-name = "3V3_ETN";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_etnphy_power>;
110 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
111 enable-active-high;
112 };
113
114 reg_2v5: regulator-2v5 {
115 compatible = "regulator-fixed";
116 regulator-name = "2V5";
117 regulator-min-microvolt = <2500000>;
118 regulator-max-microvolt = <2500000>;
119 regulator-always-on;
120 };
121
122 reg_3v3: regulator-3v3 {
123 compatible = "regulator-fixed";
124 regulator-name = "3V3";
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
127 regulator-always-on;
128 };
129
130 reg_can_xcvr: regulator-can-xcvr {
131 compatible = "regulator-fixed";
132 regulator-name = "CAN XCVR";
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
137 gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
138 };
139
140 reg_lcd0_pwr: regulator-lcd0-pwr {
141 compatible = "regulator-fixed";
142 regulator-name = "LCD0 POWER";
143 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_lcd0_pwr>;
147 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
148 enable-active-high;
149 status = "disabled";
150 };
151
152 reg_lcd1_pwr: regulator-lcd1-pwr {
153 compatible = "regulator-fixed";
154 regulator-name = "LCD1 POWER";
155 regulator-min-microvolt = <3300000>;
156 regulator-max-microvolt = <3300000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_lcd1_pwr>;
159 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
160 enable-active-high;
161 status = "disabled";
162 };
163
164 reg_usbh1_vbus: regulator-usbh1-vbus {
165 compatible = "regulator-fixed";
166 regulator-name = "usbh1_vbus";
167 regulator-min-microvolt = <5000000>;
168 regulator-max-microvolt = <5000000>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_usbh1_vbus>;
171 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
172 enable-active-high;
173 };
174
175 reg_usbotg_vbus: regulator-usbotg-vbus {
176 compatible = "regulator-fixed";
177 regulator-name = "usbotg_vbus";
178 regulator-min-microvolt = <5000000>;
179 regulator-max-microvolt = <5000000>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usbotg_vbus>;
182 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
183 enable-active-high;
184 };
185
186 sound {
187 compatible = "karo,imx6qdl-tx6-sgtl5000",
188 "simple-audio-card";
189 simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_audmux>;
192 simple-audio-card,format = "i2s";
193 simple-audio-card,bitclock-master = <&codec_dai>;
194 simple-audio-card,frame-master = <&codec_dai>;
195 simple-audio-card,widgets =
196 "Microphone", "Mic Jack",
197 "Line", "Line In",
198 "Line", "Line Out",
199 "Headphone", "Headphone Jack";
200 simple-audio-card,routing =
201 "MIC_IN", "Mic Jack",
202 "Mic Jack", "Mic Bias",
203 "Headphone Jack", "HP_OUT";
204
205 cpu_dai: simple-audio-card,cpu {
206 sound-dai = <&ssi1>;
207 };
208
209 codec_dai: simple-audio-card,codec {
210 sound-dai = <&sgtl5000>;
211 };
212 };
213};
214
215&audmux {
216 status = "okay";
217
218 mux-ssi1 {
219 fsl,audmux-port = <0>;
220 fsl,port-config = <
221 (IMX_AUDMUX_V2_PTCR_SYN |
222 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
223 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
224 IMX_AUDMUX_V2_PTCR_TFSDIR |
225 IMX_AUDMUX_V2_PTCR_TCLKDIR)
226 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
227 >;
228 };
229
230 mux-pins5 {
231 fsl,audmux-port = <4>;
232 fsl,port-config = <
233 IMX_AUDMUX_V2_PTCR_SYN
234 IMX_AUDMUX_V2_PDCR_RXDSEL(0)
235 >;
236 };
237};
238
239&can1 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_flexcan1>;
242 xceiver-supply = <&reg_can_xcvr>;
243 status = "okay";
244};
245
246&can2 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_flexcan2>;
249 xceiver-supply = <&reg_can_xcvr>;
250 status = "okay";
251};
252
253&ecspi1 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_ecspi1>;
256 cs-gpios = <
257 &gpio2 30 GPIO_ACTIVE_HIGH
258 &gpio3 19 GPIO_ACTIVE_HIGH
259 >;
260 status = "disabled";
261};
262
263&fec {
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>;
266 phy-mode = "rmii";
267 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
268 phy-reset-post-delay = <10>;
269 phy-handle = <&etnphy>;
270 phy-supply = <&reg_3v3_etn>;
271 status = "okay";
272
273 mdio {
274 #address-cells = <1>;
275 #size-cells = <0>;
276
277 etnphy: ethernet-phy@0 {
278 compatible = "ethernet-phy-ieee802.3-c22";
279 reg = <0>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_etnphy_int>;
282 interrupt-parent = <&gpio7>;
283 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
284 };
285 };
286};
287
288&gpmi {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_gpmi_nand>;
291 nand-on-flash-bbt;
292 fsl,no-blockmark-swap;
293 status = "okay";
294};
295
296&i2c1 {
297 pinctrl-names = "default", "gpio";
298 pinctrl-0 = <&pinctrl_i2c1>;
299 pinctrl-1 = <&pinctrl_i2c1_gpio>;
300 scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
301 sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
302 clock-frequency = <400000>;
303 status = "okay";
304
305 ds1339: rtc@68 {
306 compatible = "dallas,ds1339";
307 reg = <0x68>;
308 trickle-resistor-ohms = <250>;
309 trickle-diode-disable;
310 };
311};
312
313&i2c3 {
314 pinctrl-names = "default", "gpio";
315 pinctrl-0 = <&pinctrl_i2c3>;
316 pinctrl-1 = <&pinctrl_i2c3_gpio>;
317 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
318 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
319 clock-frequency = <400000>;
320 status = "okay";
321
322 sgtl5000: sgtl5000@a {
323 compatible = "fsl,sgtl5000";
324 #sound-dai-cells = <0>;
325 reg = <0x0a>;
326 VDDA-supply = <&reg_2v5>;
327 VDDIO-supply = <&reg_3v3>;
328 clocks = <&mclk>;
329 };
330
331 polytouch: edt-ft5x06@38 {
332 compatible = "edt,edt-ft5x06";
333 reg = <0x38>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_edt_ft5x06>;
336 interrupt-parent = <&gpio6>;
337 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
338 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
339 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
340 wakeup-source;
341 };
342
343 touchscreen: tsc2007@48 {
344 compatible = "ti,tsc2007";
345 reg = <0x48>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_tsc2007>;
348 interrupt-parent = <&gpio3>;
349 interrupts = <26 0>;
350 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
351 ti,x-plate-ohms = <660>;
352 wakeup-source;
353 };
354};
355
356&iomuxc {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_hog>;
359
360 pinctrl_hog: hoggrp {
361 fsl,pins = <
362 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
363 >;
364 };
365
366 pinctrl_audmux: audmuxgrp {
367 fsl,pins = <
368 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
369 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
370 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
371 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
372 >;
373 };
374
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]375 pinctrl_disp0_1: disp0-1-grp {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]376 fsl,pins = <
377 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
378 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
379 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
380 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
381 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
382 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
383 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
384 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
385 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
386 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
387 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
388 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
389 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
390 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
391 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
392 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
393 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
394 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
395 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
396 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
397 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
398 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
399 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
400 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
401 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
402 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
403 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
404 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
405 >;
406 };
407
Tom Rini9c8af152024-12-24 12:03:04 -0600[diff] [blame]408 pinctrl_disp0_2: disp0-2-grp {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]409 fsl,pins = <
410 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
411 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
412 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
413 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
414 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
415 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
416 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
417 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
418 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
419 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
420 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
421 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
422 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
423 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
424 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
425 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
426 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
427 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
428 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
429 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
430 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
431 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
432 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
433 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
434 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
435 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
436 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
437 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
438 >;
439 };
440
441 pinctrl_ecspi1: ecspi1grp {
442 fsl,pins = <
443 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
444 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
445 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
446 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
447 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
448 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
449 >;
450 };
451
452 pinctrl_edt_ft5x06: edt-ft5x06grp {
453 fsl,pins = <
454 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
455 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
456 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
457 >;
458 };
459
460 pinctrl_enet: enetgrp {
461 fsl,pins = <
462 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
463 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
464 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
465 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
466 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
467 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
468 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
469 >;
470 };
471
472 pinctrl_enet_mdio: enet-mdiogrp {
473 fsl,pins = <
474 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
475 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
476 >;
477 };
478
479 pinctrl_etnphy_int: etnphy-intgrp {
480 fsl,pins = <
481 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
482 >;
483 };
484
485 pinctrl_etnphy_power: etnphy-pwrgrp {
486 fsl,pins = <
487 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
488 >;
489 };
490
491 pinctrl_etnphy_rst: etnphy-rstgrp {
492 fsl,pins = <
493 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
494 >;
495 };
496
497 pinctrl_flexcan1: flexcan1grp {
498 fsl,pins = <
499 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
500 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
501 >;
502 };
503
504 pinctrl_flexcan2: flexcan2grp {
505 fsl,pins = <
506 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
507 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
508 >;
509 };
510
511 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
512 fsl,pins = <
513 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
514 >;
515 };
516
517 pinctrl_gpmi_nand: gpminandgrp {
518 fsl,pins = <
519 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
520 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
521 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
522 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
523 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
524 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
525 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
526 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
527 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
528 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
529 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
530 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
531 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
532 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
533 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
534 >;
535 };
536
537 pinctrl_i2c1: i2c1grp {
538 fsl,pins = <
539 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
540 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
541 >;
542 };
543
544 pinctrl_i2c1_gpio: i2c1-gpiogrp {
545 fsl,pins = <
546 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
547 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
548 >;
549 };
550
551 pinctrl_i2c3: i2c3grp {
552 fsl,pins = <
553 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
554 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
555 >;
556 };
557
558 pinctrl_i2c3_gpio: i2c3-gpiogrp {
559 fsl,pins = <
560 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
561 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
562 >;
563 };
564
565 pinctrl_kpp: kppgrp {
566 fsl,pins = <
567 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
568 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
569 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
570 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
571 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
572 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
573 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
574 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
575 >;
576 };
577
578 pinctrl_lcd0_pwr: lcd0-pwrgrp {
579 fsl,pins = <
580 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
581 >;
582 };
583
584 pinctrl_lcd1_pwr: lcd-pwrgrp {
585 fsl,pins = <
586 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
587 >;
588 };
589
590 pinctrl_pwm1: pwm1grp {
591 fsl,pins = <
592 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
593 >;
594 };
595
596 pinctrl_pwm2: pwm2grp {
597 fsl,pins = <
598 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
599 >;
600 };
601
602 pinctrl_tsc2007: tsc2007grp {
603 fsl,pins = <
604 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
605 >;
606 };
607
608 pinctrl_uart1: uart1grp {
609 fsl,pins = <
610 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
611 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
612 >;
613 };
614
615 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
616 fsl,pins = <
617 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
618 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
619 >;
620 };
621
622 pinctrl_uart2: uart2grp {
623 fsl,pins = <
624 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
625 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
626 >;
627 };
628
629 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
630 fsl,pins = <
631 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
632 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
633 >;
634 };
635
636 pinctrl_uart3: uart3grp {
637 fsl,pins = <
638 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
639 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
640 >;
641 };
642
643 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
644 fsl,pins = <
645 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
646 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
647 >;
648 };
649
650 pinctrl_usbh1_vbus: usbh1-vbusgrp {
651 fsl,pins = <
652 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
653 >;
654 };
655
656 pinctrl_usbotg: usbotggrp {
657 fsl,pins = <
658 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
659 >;
660 };
661
662 pinctrl_usbotg_vbus: usbotg-vbusgrp {
663 fsl,pins = <
664 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
665 >;
666 };
667
668 pinctrl_usdhc1: usdhc1grp {
669 fsl,pins = <
670 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
671 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
672 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
673 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
674 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
675 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
676 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
677 >;
678 };
679
680 pinctrl_usdhc2: usdhc2grp {
681 fsl,pins = <
682 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
683 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
684 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
685 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
686 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
687 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
688 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
689 >;
690 };
691
692 pinctrl_user_led: user-ledgrp {
693 fsl,pins = <
694 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
695 >;
696 };
697};
698
699&kpp {
700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_kpp>;
702 /* sample keymap */
703 /* row/col 0,1 are mapped to KPP row/col 6,7 */
704 linux,keymap = <
705 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
706 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
707 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
708 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
709 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
710 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
711 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
712 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
713 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
714 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
715 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
716 >;
717 status = "okay";
718};
719
720&pwm1 {
721 pinctrl-names = "default";
722 pinctrl-0 = <&pinctrl_pwm1>;
723 status = "disabled";
724};
725
726&pwm2 {
727 pinctrl-names = "default";
728 pinctrl-0 = <&pinctrl_pwm2>;
729 status = "okay";
730};
731
732&ssi1 {
733 status = "okay";
734};
735
736&uart1 {
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
739 uart-has-rtscts;
740 status = "okay";
741};
742
743&uart2 {
744 pinctrl-names = "default";
745 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
746 uart-has-rtscts;
747 status = "okay";
748};
749
750&uart3 {
751 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
753 uart-has-rtscts;
754 status = "okay";
755};
756
757&usbh1 {
758 vbus-supply = <&reg_usbh1_vbus>;
759 dr_mode = "host";
760 disable-over-current;
761 status = "okay";
762};
763
764&usbotg {
765 vbus-supply = <&reg_usbotg_vbus>;
766 pinctrl-names = "default";
767 pinctrl-0 = <&pinctrl_usbotg>;
768 dr_mode = "peripheral";
769 disable-over-current;
770 status = "okay";
771};
772
773&usdhc1 {
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_usdhc1>;
776 bus-width = <4>;
777 no-1-8-v;
778 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
779 fsl,wp-controller;
780 status = "okay";
781};
782
783&usdhc2 {
784 pinctrl-names = "default";
785 pinctrl-0 = <&pinctrl_usdhc2>;
786 bus-width = <4>;
787 no-1-8-v;
788 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
789 fsl,wp-controller;
790 status = "okay";
791};