blob: 6210673f93bea67c4f717b11439069d86f90b008 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 Marek Vasut <marex@denx.de>
4 */
5
6/dts-v1/;
7#include "imx53-m53.dtsi"
8
9/ {
10 model = "MENLO M53 EMBEDDED DEVICE";
11 compatible = "menlo,m53menlo", "fsl,imx53";
12
13 gpio-keys {
14 compatible = "gpio-keys";
15 pinctrl-0 = <&pinctrl_power_button>;
16 pinctrl-names = "default";
17
18 power-button {
19 label = "Power button";
20 gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
21 linux,code = <KEY_POWER>;
22 };
23 };
24
25 gpio-poweroff {
26 compatible = "gpio-poweroff";
27 pinctrl-0 = <&pinctrl_power_out>;
28 pinctrl-names = "default";
29 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
30 };
31
32 leds {
33 compatible = "gpio-leds";
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_led>;
36
37 led-user1 {
38 label = "TestLed601";
39 gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
40 linux,default-trigger = "mmc0";
41 };
42
43 led-user2 {
44 label = "TestLed602";
45 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
46 linux,default-trigger = "heartbeat";
47 };
48
49 led-eth {
50 label = "EthLedYe";
51 gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
52 linux,default-trigger = "netdev";
53 };
54 };
55
56 lvds-decoder {
57 compatible = "ti,ds90cf364a", "lvds-decoder";
58
59 ports {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 port@0 {
64 reg = <0>;
65
66 lvds_decoder_in: endpoint {
Tom Rini6b642ac2024-10-01 12:20:28 -060067 data-mapping = "jeida-18";
Tom Rini53633a82024-02-29 12:33:36 -050068 remote-endpoint = <&lvds0_out>;
69 };
70 };
71
72 port@1 {
73 reg = <1>;
74
75 lvds_decoder_out: endpoint {
76 remote-endpoint = <&panel_in>;
77 };
78 };
79 };
80 };
81
82 panel {
83 compatible = "edt,etm0700g0dh6";
84 pinctrl-0 = <&pinctrl_display_gpio>;
85 pinctrl-names = "default";
86 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
87
88 port {
89 panel_in: endpoint {
90 remote-endpoint = <&lvds_decoder_out>;
91 };
92 };
93 };
94
95 beeper {
96 compatible = "gpio-beeper";
97 pinctrl-0 = <&pinctrl_beeper>;
98 gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
99 };
100
101 reg_usbh1_vbus: regulator-usbh1-vbus {
102 compatible = "regulator-fixed";
103 regulator-name = "vbus";
104 regulator-min-microvolt = <5000000>;
105 regulator-max-microvolt = <5000000>;
106 gpio = <&gpio1 2 0>;
107 };
108};
109
110&can1 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_can1>;
113 status = "okay";
114};
115
116&can2 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_can2>;
119 status = "okay";
120};
121
122&clks {
123 assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>,
124 <&clks IMX5_CLK_CKO1_PODF>,
125 <&clks IMX5_CLK_CKO1>;
126 assigned-clock-parents = <&clks IMX5_CLK_AHB>;
127 assigned-clock-rates = <133333334>, <33333334>, <33333334>;
128};
129
130&ecspi2 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ecspi2>;
133 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>;
134 status = "okay";
135
136 spidev@0 {
137 compatible = "menlo,m53cpld";
138 spi-max-frequency = <25000000>;
139 reg = <0>;
140 };
141
142 spidev@1 {
143 compatible = "menlo,m53cpld";
144 spi-max-frequency = <25000000>;
145 reg = <1>;
146 };
147};
148
149&esdhc1 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_esdhc1>;
152 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
153 wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
154 status = "okay";
155};
156
157&fec {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_fec>;
160 phy-mode = "rmii";
161 phy-reset-gpios = <&gpio7 7 GPIO_ACTIVE_LOW>;
162 status = "okay";
163};
164
165&gpio1 {
166 gpio-line-names =
167 "", "", "", "",
168 "", "", "", "",
169 "", "", "", "",
170 "", "", "", "",
171 "", "", "", "",
172 "", "", "", "",
173 "", "", "", "",
174 "", "", "", "";
175};
176
177&gpio2 {
178 gpio-line-names =
179 "", "", "", "",
180 "", "", "", "",
181 "TestPin_SV2_3", "", "", "",
182 "", "", "", "",
183 "", "", "", "",
184 "", "", "", "",
185 "", "", "", "",
186 "", "", "", "";
187};
188
189&gpio3 {
190 gpio-line-names =
191 "", "", "", "",
192 "", "", "", "",
193 "", "", "", "",
194 "", "", "", "",
195 "", "", "", "",
196 "", "", "", "",
197 "CPLD_JTAG_TDI", "CPLD_JTAG_TMS", "", "",
198 "", "CPLD_JTAG_TDO", "", "";
199};
200
201&gpio5 {
202 gpio-line-names =
203 "", "", "", "",
204 "", "", "", "",
205 "", "", "", "",
206 "", "", "", "",
207 "", "", "CPLD_JTAG_TCK", "KBD_intK",
208 "CPLD_int", "CPLD_JTAG_internal", "CPLD_D[0]", "CPLD_D[1]",
209 "CPLD_D[2]", "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]",
210 "CPLD_D[6]", "CPLD_D[7]", "DISP_reset", "KBD_intI";
211};
212
213&gpio6 {
214 gpio-line-names =
215 "", "", "", "",
216 "CPLD_reset", "", "", "",
217 "", "", "", "",
218 "", "", "", "",
219 "", "", "", "",
220 "", "", "", "",
221 "", "", "", "",
222 "", "", "", "";
223};
224
225&gpio7 {
226 gpio-line-names =
227 "", "", "", "",
228 "", "", "", "",
229 "", "", "", "",
230 "", "USB-OTG_OverCurrent", "", "",
231 "", "", "", "",
232 "", "", "", "",
233 "", "", "", "",
234 "", "", "", "";
235};
236
237&i2c1 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c1>;
240 status = "okay";
241
242 touchscreen@38 {
243 compatible = "edt,edt-ft5x06";
244 reg = <0x38>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_edt_ft5x06>;
247 interrupt-parent = <&gpio6>;
248 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
249 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
250 wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
251 };
252
253 eeprom@50 {
254 compatible = "atmel,24c64";
255 reg = <0x50>;
256 pagesize = <32>;
257 };
258
259 dac@60 {
260 compatible = "microchip,mcp4725";
261 reg = <0x60>;
262 };
263};
264
265&i2c2 {
266 touchscreen@41 {
267 status = "disabled";
268 };
269};
270
271&i2c3 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_i2c3>;
274 status = "okay";
275};
276
277&iomuxc {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_hog>;
280
Tom Rini844493d2025-01-26 16:17:47 -0600281 hoggrp {
282 fsl,pins = <
283 MX53_PAD_GPIO_19__CCM_CLKO 0x1e4
284 MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4
285 MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4
286 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4
287 MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4
288 MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4
289 MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4
290 MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4
291 MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4
292 MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4
293 MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4
294 MX53_PAD_EIM_D24__GPIO3_24 0x1e4
295 MX53_PAD_EIM_D25__GPIO3_25 0x1e4
296 MX53_PAD_EIM_D29__GPIO3_29 0x1e4
297 MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4
298 MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4
299 MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4
300 MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4
301 >;
302 };
Tom Rini53633a82024-02-29 12:33:36 -0500303
Tom Rini844493d2025-01-26 16:17:47 -0600304 pinctrl_led: ledgrp {
305 fsl,pins = <
306 MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4
307 MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4
308 >;
309 };
Tom Rini53633a82024-02-29 12:33:36 -0500310
Tom Rini844493d2025-01-26 16:17:47 -0600311 pinctrl_beeper: beepergrp {
312 fsl,pins = <
313 MX53_PAD_CSI0_DAT17__GPIO6_3 0x1c4
314 >;
315 };
Tom Rini53633a82024-02-29 12:33:36 -0500316
Tom Rini844493d2025-01-26 16:17:47 -0600317 pinctrl_can1: can1grp {
318 fsl,pins = <
319 MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4
320 MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4
321 >;
322 };
Tom Rini53633a82024-02-29 12:33:36 -0500323
Tom Rini844493d2025-01-26 16:17:47 -0600324 pinctrl_can2: can2grp {
325 fsl,pins = <
326 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4
327 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
328 >;
329 };
Tom Rini53633a82024-02-29 12:33:36 -0500330
Tom Rini844493d2025-01-26 16:17:47 -0600331 pinctrl_display_gpio: display-gpiogrp {
332 fsl,pins = <
333 MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */
334 MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */
335 MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */
Tom Rini53633a82024-02-29 12:33:36 -0500336
Tom Rini844493d2025-01-26 16:17:47 -0600337 MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */
338 >;
339 };
Tom Rini53633a82024-02-29 12:33:36 -0500340
Tom Rini844493d2025-01-26 16:17:47 -0600341 pinctrl_edt_ft5x06: edt-ft5x06grp {
342 fsl,pins = <
343 MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */
344 MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */
345 MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */
346 >;
347 };
Tom Rini53633a82024-02-29 12:33:36 -0500348
Tom Rini844493d2025-01-26 16:17:47 -0600349 pinctrl_ecspi2: ecspi2grp {
350 fsl,pins = <
351 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0xe4
352 MX53_PAD_EIM_OE__ECSPI2_MISO 0xe4
353 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0xe4
354 MX53_PAD_EIM_RW__GPIO2_26 0xe4
355 MX53_PAD_EIM_LBA__GPIO2_27 0xe4
356 >;
357 };
Tom Rini53633a82024-02-29 12:33:36 -0500358
Tom Rini844493d2025-01-26 16:17:47 -0600359 pinctrl_esdhc1: esdhc1grp {
360 fsl,pins = <
361 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4
362 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4
363 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4
364 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4
365 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4
366 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4
367 MX53_PAD_GPIO_1__GPIO1_1 0x1c4
368 MX53_PAD_GPIO_9__GPIO1_9 0x1e4
369 >;
370 };
Tom Rini53633a82024-02-29 12:33:36 -0500371
Tom Rini844493d2025-01-26 16:17:47 -0600372 pinctrl_fec: fecgrp {
373 fsl,pins = <
374 MX53_PAD_FEC_MDC__FEC_MDC 0x1e4
375 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4
376 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4
377 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4
378 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4
379 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4
380 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4
381 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4
382 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4
383 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4
384 MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4
385 MX53_PAD_EIM_EB3__GPIO2_31 0x1e4
386 >;
387 };
Tom Rini53633a82024-02-29 12:33:36 -0500388
Tom Rini844493d2025-01-26 16:17:47 -0600389 pinctrl_i2c1: i2c1grp {
390 fsl,pins = <
391 MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
392 MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
393 >;
394 };
Tom Rini53633a82024-02-29 12:33:36 -0500395
Tom Rini844493d2025-01-26 16:17:47 -0600396 pinctrl_i2c3: i2c3grp {
397 fsl,pins = <
398 MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4
399 MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4
400 >;
401 };
Tom Rini53633a82024-02-29 12:33:36 -0500402
Tom Rini844493d2025-01-26 16:17:47 -0600403 pinctrl_lvds0: lvds0grp {
404 /* LVDS pins only have pin mux configuration */
405 fsl,pins = <
406 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
407 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
408 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
409 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
410 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
411 >;
412 };
Tom Rini53633a82024-02-29 12:33:36 -0500413
Tom Rini844493d2025-01-26 16:17:47 -0600414 pinctrl_power_button: powerbutgrp {
415 fsl,pins = <
416 MX53_PAD_SD2_DATA0__GPIO1_15 0x1e4
417 >;
418 };
Tom Rini53633a82024-02-29 12:33:36 -0500419
Tom Rini844493d2025-01-26 16:17:47 -0600420 pinctrl_power_out: poweroutgrp {
421 fsl,pins = <
422 MX53_PAD_SD2_DATA2__GPIO1_13 0x1e4
423 >;
424 };
Tom Rini53633a82024-02-29 12:33:36 -0500425
Tom Rini844493d2025-01-26 16:17:47 -0600426 pinctrl_uart1: uart1grp {
427 fsl,pins = <
428 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
429 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
430 MX53_PAD_PATA_IORDY__UART1_RTS 0x1e4
431 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1e4
432 >;
433 };
Tom Rini53633a82024-02-29 12:33:36 -0500434
Tom Rini844493d2025-01-26 16:17:47 -0600435 pinctrl_uart2: uart2grp {
436 fsl,pins = <
437 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
438 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
439 MX53_PAD_PATA_DIOR__UART2_RTS 0x1e4
440 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1e4
441 >;
442 };
Tom Rini53633a82024-02-29 12:33:36 -0500443
Tom Rini844493d2025-01-26 16:17:47 -0600444 pinctrl_uart3: uart3grp {
445 fsl,pins = <
446 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
447 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
448 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
449 >;
450 };
Tom Rini53633a82024-02-29 12:33:36 -0500451
Tom Rini844493d2025-01-26 16:17:47 -0600452 pinctrl_usb: usbgrp {
453 fsl,pins = <
454 MX53_PAD_GPIO_2__GPIO1_2 0x1c4
455 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1c4
456 MX53_PAD_GPIO_4__GPIO1_4 0x1c4
457 MX53_PAD_GPIO_18__GPIO7_13 0x1c4
458 >;
Tom Rini53633a82024-02-29 12:33:36 -0500459 };
460};
461
462&ldb {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_lvds0>;
465 status = "okay";
466
467 lvds0: lvds-channel@0 {
468 reg = <0>;
469 fsl,data-mapping = "spwg";
470 fsl,data-width = <18>;
471 status = "okay";
472
473 port@2 {
474 reg = <2>;
475
476 lvds0_out: endpoint {
477 remote-endpoint = <&lvds_decoder_in>;
478 };
479 };
480 };
481};
482
483&uart1 {
484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_uart1>;
486 uart-has-rtscts;
487 status = "okay";
488};
489
490&uart2 {
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_uart2>;
493 uart-has-rtscts;
494 status = "okay";
495};
496
497&uart3 {
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_uart3>;
500 linux,rs485-enabled-at-boot-time;
501 status = "okay";
502};
503
504&usbh1 {
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_usb>;
507 vbus-supply = <&reg_usbh1_vbus>;
508 phy_type = "utmi";
509 dr_mode = "host";
510 status = "okay";
511};
512
513&usbotg {
514 dr_mode = "peripheral";
515 status = "okay";
516};