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git01.mediatek.com / filogic / uboot / 5e6fe8b51a6519628375f15d9ae42917b1c4fc39 / . / drivers / clk / sunxi / clk_a100.c
blob: b641feb8612ab831c96a84dbd5960caf38caf98b [file] [log] [blame]
Andre Przywarac0459ea2023-10-26 00:28:44 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2023-2024 Arm Ltd.
4 */
5
6#include <clk/sunxi.h>
7#include <dt-bindings/clock/sun50i-a100-ccu.h>
8#include <dt-bindings/reset/sun50i-a100-ccu.h>
9#include <linux/bitops.h>
10
11static struct ccu_clk_gate a100_gates[] = {
12 [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
13
14 [CLK_APB1] = GATE_DUMMY,
15
16 [CLK_DE] = GATE(0x600, BIT(31)),
17 [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
18
19 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
20 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
21 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
22
23 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
24 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
25 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
26 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
27 [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
28
29 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
30 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
31 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
32 [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
33
34 [CLK_SPI0] = GATE(0x940, BIT(31)),
35 [CLK_SPI1] = GATE(0x944, BIT(31)),
36 [CLK_SPI2] = GATE(0x948, BIT(31)),
37
38 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
39 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
40 [CLK_BUS_SPI2] = GATE(0x96c, BIT(2)),
41
42 [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
43
44 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
45 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
46
47 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
48 [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
49
50 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
51 [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
52 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
53 [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
54 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
55
56 [CLK_TCON_LCD] = GATE(0xb60, BIT(31)),
57 [CLK_BUS_TCON_LCD] = GATE(0xb7c, BIT(0)),
58};
59
60static struct ccu_reset a100_resets[] = {
61 [RST_BUS_DE] = RESET(0x60c, BIT(16)),
62
63 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
64 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
65 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
66
67 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
68 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
69 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
70 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
71 [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
72
73 [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
74 [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
75 [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
76 [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
77
78 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
79 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
80 [RST_BUS_SPI2] = RESET(0x96c, BIT(18)),
81
82 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
83
84 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
85
86 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
87
88 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
89 [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
90 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
91 [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
92 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
93
94 [RST_BUS_TCON_LCD] = RESET(0xb7c, BIT(16)),
95};
96
97const struct ccu_desc a100_ccu_desc = {
98 .gates = a100_gates,
99 .resets = a100_resets,
100 .num_gates = ARRAY_SIZE(a100_gates),
101 .num_resets = ARRAY_SIZE(a100_resets),
102};