| Svyatoslav Ryhel | df7c418 | 2024-11-16 14:33:47 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Mocha SPL stage configuration |
| 4 | * |
| 5 | * (C) Copyright 2024 |
| 6 | * Svyatoslav Ryhel <clamor95@gmail.com> |
| 7 | */ |
| 8 | |
| 9 | #include <asm/arch/tegra.h> |
| 10 | #include <asm/arch-tegra/tegra_i2c.h> |
| 11 | #include <linux/delay.h> |
| 12 | |
| 13 | #define TPS65913_I2C_ADDR (0x58 << 1) |
| 14 | |
| 15 | #define TPS65913_SMPS12_CTRL 0x20 |
| 16 | #define TPS65913_SMPS12_VOLTAGE 0x23 |
| 17 | #define TPS65913_SMPS45_CTRL 0x28 |
| 18 | #define TPS65913_SMPS45_VOLTAGE 0x2B |
| 19 | #define TPS65913_SMPS7_CTRL 0x30 |
| 20 | #define TPS65913_SMPS7_VOLTAGE 0x33 |
| 21 | |
| 22 | #define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) |
| 23 | #define TPS65913_SMPS12_VOLTAGE_DATA (0x3800 | TPS65913_SMPS12_VOLTAGE) |
| 24 | #define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) |
| 25 | #define TPS65913_SMPS45_VOLTAGE_DATA (0x3800 | TPS65913_SMPS45_VOLTAGE) |
| 26 | #define TPS65913_SMPS7_CTRL_DATA (0x5100 | TPS65913_SMPS7_CTRL) |
| 27 | #define TPS65913_SMPS7_VOLTAGE_DATA (0x4700 | TPS65913_SMPS7_VOLTAGE) |
| 28 | |
| 29 | void pmic_enable_cpu_vdd(void) |
| 30 | { |
| 31 | /* Set CORE VDD to 1.150V. */ |
| 32 | tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS7_VOLTAGE_DATA); |
| 33 | udelay(1000); |
| 34 | tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS7_CTRL_DATA); |
| 35 | |
| 36 | udelay(1000); |
| 37 | |
| 38 | /* Set CPU VDD to 1.0V. */ |
| 39 | tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); |
| 40 | udelay(1000); |
| 41 | tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); |
| 42 | udelay(10 * 1000); |
| 43 | |
| 44 | /* Set GPU VDD to 1.0V. */ |
| 45 | tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); |
| 46 | udelay(1000); |
| 47 | tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); |
| 48 | udelay(10 * 1000); |
| 49 | } |