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wdenkbb1b8262003-03-27 12:09:35 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the INCA-IP board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
32#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
33
wdenk92bbe3f2003-04-20 14:04:18 +000034/* allowed values: 100000000, 133000000, and 150000000 */
wdenka5ae1f02003-07-31 22:56:30 +000035#define CPU_CLOCK_RATE 133000000 /* 133 MHz clock for the MIPS core */
wdenkbb1b8262003-03-27 12:09:35 +000036
wdenkb02744a2003-04-05 00:53:31 +000037#if CPU_CLOCK_RATE == 100000000
38#define INFINEON_EBU_BOOTCFG 0x20C4 /* CMULT = 4 for 100 MHz */
39#else
40#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 for 150 MHz */
41#endif
wdenkbb1b8262003-03-27 12:09:35 +000042
wdenkbb1b8262003-03-27 12:09:35 +000043
wdenkb02744a2003-04-05 00:53:31 +000044#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkbb1b8262003-03-27 12:09:35 +000045
wdenkb02744a2003-04-05 00:53:31 +000046#define CONFIG_BAUDRATE 115200
wdenkbb1b8262003-03-27 12:09:35 +000047
48/* valid baudrates */
49#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
50
wdenkb02744a2003-04-05 00:53:31 +000051#define CONFIG_TIMESTAMP /* Print image info with timestamp */
52
53#define CONFIG_PREBOOT "echo;" \
54 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
55 "echo"
56
57#undef CONFIG_BOOTARGS
58
59#define CONFIG_EXTRA_ENV_SETTINGS \
60 "nfsargs=setenv bootargs root=/dev/nfs rw " \
61 "nfsroot=$(serverip):$(rootpath)\0" \
62 "ramargs=setenv bootargs root=/dev/ram rw\0" \
63 "addip=setenv bootargs $(bootargs) " \
64 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
65 ":$(hostname):$(netdev):off\0" \
66 "addmisc=setenv bootargs $(bootargs) " \
67 "console=ttyS0,$(baudrate) " \
68 "ethaddr=$(ethaddr) " \
69 "panic=1\0" \
70 "flash_nfs=run nfsargs addip addmisc;" \
71 "bootm $(kernel_addr)\0" \
72 "flash_self=run ramargs addip addmisc;" \
73 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
74 "net_nfs=tftp 80500000 $(bootfile);" \
75 "run nfsargs addip addmisc;bootm\0" \
76 "rootpath=/opt/eldk/mips_4KC\0" \
77 "bootfile=/tftpboot/INCA/uImage\0" \
78 "kernel_addr=B0040000\0" \
79 "ramdisk_addr=B0100000\0" \
80 "u-boot=/tftpboot/INCA/u-boot.bin\0" \
81 "load=tftp 80500000 $(u-boot)\0" \
82 "update=protect off 1:0-2;era 1:0-2;" \
83 "cp.b 80500000 B0000000 $(filesize)\0" \
84 ""
85#define CONFIG_BOOTCOMMAND "run flash_self"
86
87#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
88 CFG_CMD_ASKENV | \
89 CFG_CMD_DHCP | \
90 CFG_CMD_ELF )
wdenkbb1b8262003-03-27 12:09:35 +000091#include <cmd_confdefs.h>
92
93/*
94 * Miscellaneous configurable options
95 */
96#define CFG_LONGHELP /* undef to save memory */
97#define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenkbb1b8262003-03-27 12:09:35 +0000100#define CFG_MAXARGS 16 /* max number of command args*/
101
wdenkb02744a2003-04-05 00:53:31 +0000102#define CFG_MALLOC_LEN 128*1024
103
104#define CFG_BOOTPARAMS_LEN 128*1024
105
106#define CFG_HZ (CPU_CLOCK_RATE/2)
107
108#define CFG_SDRAM_BASE 0x80000000
109
wdenkbb1b8262003-03-27 12:09:35 +0000110#define CFG_LOAD_ADDR 0x80100000 /* default load address */
111
wdenkb02744a2003-04-05 00:53:31 +0000112#define CFG_MEMTEST_START 0x80100000
wdenkbb1b8262003-03-27 12:09:35 +0000113#define CFG_MEMTEST_END 0x80800000
114
115/*-----------------------------------------------------------------------
116 * FLASH and environment organization
117 */
118#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
119#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
120
121#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
122#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
123
124/* The following #defines are needed to get flash environment right */
125#define CFG_MONITOR_BASE TEXT_BASE
126#define CFG_MONITOR_LEN (192 << 10)
127
128#define CFG_INIT_SP_OFFSET 0x400000
129
130#define CFG_FLASH_BASE PHYS_FLASH_1
131
132/* timeout values are in ticks */
133#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
134#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
135
136#define CFG_ENV_IS_IN_FLASH 1
137
138/* Address and size of Primary Environment Sector */
139#define CFG_ENV_ADDR 0xB0030000
140#define CFG_ENV_SIZE 0x10000
141
142#define CONFIG_FLASH_16BIT
143
144#define CONFIG_NR_DRAM_BANKS 1
145
146#define CONFIG_INCA_IP_SWITCH
147#define CONFIG_NET_MULTI
148
149/*-----------------------------------------------------------------------
150 * Cache Configuration
151 */
152#define CFG_DCACHE_SIZE 4096
153#define CFG_ICACHE_SIZE 4096
154#define CFG_CACHELINE_SIZE 16
155
156#endif /* __CONFIG_H */