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git01.mediatek.com / filogic / uboot / 5d32dbd355714a10640e0b0d6518afad83bed51d / . / board / ep8248 / ep8248.c
blob: 736c1806d159f1d8bfed0e8994b129028e409cdf [file] [log] [blame]
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]1/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Embedded Planet EP8248 boards.
6 * Tested on EP8248E.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]9 */
10
11#include <common.h>
12#include <mpc8260.h>
13#include <ioports.h>
14
15/*
16 * I/O Port configuration table
17 *
18 * if conf is 1, then that port pin will be configured at boot time
19 * according to the five values podr/pdir/ppar/psor/pdat for that entry
20 */
21
Marcel Ziswilerbf127132009-09-09 21:22:08 +0200[diff] [blame]22#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
23#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]24
25const iop_conf_t iop_conf_tab[4][32] = {
26
27 /* Port A */
28 { /* conf ppar psor pdir podr pdat */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]29 /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
30 /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
31 /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
32 /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
33 /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
34 /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]35 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
36 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
37 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
38 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]39 /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
40 /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
41 /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
42 /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
43 /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
44 /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
45 /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
46 /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]47 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
48 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
49 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
50 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
51 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
52 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
53 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
54 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
55 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
56 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
57 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
58 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
59 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
60 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
61 },
62
63 /* Port B */
64 { /* conf ppar psor pdir podr pdat */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]65 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
66 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
67 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
68 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
69 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
70 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
71 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
72 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
73 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
74 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
75 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
76 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
77 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
78 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]79 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
80 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
81 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
82 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
83 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
84 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
85 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
86 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
87 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
88 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
89 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
90 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
91 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
92 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
93 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
94 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
95 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
96 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
97 },
98
99 /* Port C */
100 { /* conf ppar psor pdir podr pdat */
101 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
102 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
103 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
104 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
105 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
106 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
107 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
108 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
109 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]110 /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */
111 /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]112 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]113 /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */
114 /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]115 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
116 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
117 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
118 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
119 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
120 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
121 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
122 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
123 /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
124 /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
125 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
126 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
127 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
128 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
129 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
130 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
131 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
132 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
133 },
134
135 /* Port D */
136 { /* conf ppar psor pdir podr pdat */
137 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
138 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
139 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
140 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
141 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
142 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
143 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
144 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
145 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
146 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
147 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
148 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
149 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
150 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
151 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
152 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
153 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
154 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
155 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
156 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
157 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
158 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
159 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
160 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
161 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
162 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
163 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
164 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
165 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
166 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
167 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
168 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
169 }
170};
171
172int board_early_init_f (void)
173{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]174 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]175
176 bcsr[4] |= 0x30; /* Turn the LEDs off */
177
178#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
179 bcsr[6] |= 0x10;
180#endif
181#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
182 bcsr[7] |= 0x10;
183#endif
184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]185#if CONFIG_SYS_FCC1
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]186 bcsr[8] |= 0xC0;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]187#endif /* CONFIG_SYS_FCC1 */
188#if CONFIG_SYS_FCC2
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]189 bcsr[8] |= 0x30;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]190#endif /* CONFIG_SYS_FCC2 */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]191
192 return 0;
193}
194
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]195phys_size_t initdram(int board_type)
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]196{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]197 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]198 long int msize = 16L << (bcsr[2] & 3);
199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]200#ifndef CONFIG_SYS_RAMBOOT
201 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]202 volatile memctl8260_t *memctl = &immap->im_memctl;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]203 vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]204 uchar c = 0xFF;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]205 uint psdmr = CONFIG_SYS_PSDMR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]206 int i;
207
208 immap->im_siu_conf.sc_ppc_acr = 0x02;
209 immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
210 immap->im_siu_conf.sc_tescr1 = 0x00004000;
211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]212 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]213
214 /* Initialise 60x bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]215 memctl->memc_psrt = CONFIG_SYS_PSRT;
216 memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
217 memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]218 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
219 *ramaddr = c;
220 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
221 for (i = 0; i < 8; i++)
222 *ramaddr = c;
223 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
224 *ramaddr = c;
225 memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
226 *ramaddr = c;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]227#endif /* !CONFIG_SYS_RAMBOOT */
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]228
229 /* Return total 60x bus SDRAM size */
230 return msize * 1024 * 1024;
231}
232
233int checkboard(void)
234{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]235 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denk8dd4d332005-08-06 01:42:58 +0200[diff] [blame]236
237 puts("Board: ");
238 switch (bcsr[0]) {
239 case 0x0C:
240 printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
241 break;
242 default:
243 printf("unknown: ID=%02X\n", bcsr[0]);
244 }
245
246 return 0;
247}
Marcel Ziswilerbf127132009-09-09 21:22:08 +0200[diff] [blame]248
249#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
250void ft_board_setup(void *blob, bd_t *bd)
251{
252 ft_cpu_setup( blob, bd);
253}
254#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */