blob: 1c4134d82753b83a0c7017dbb6ac417201815991 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -04002/*
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
6 * original copyright follows:
7 * Copyright 2011 Freescale Semiconductor, Inc.
Oleksandr G Zhadan19ac6882015-04-29 16:57:39 -04008 */
9
10#include <common.h>
11#include <ns16550.h>
12#include <asm/io.h>
13#include <nand.h>
14#include <linux/compiler.h>
15#include <asm/fsl_law.h>
16#include <fsl_ddr_sdram.h>
17#include <asm/global_data.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21void board_init_f(ulong bootflag)
22{
23 u32 plat_ratio;
24 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
25
26#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
27 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
28 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
29#endif
30
31 /* initialize selected port with appropriate baud rate */
32 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
33 plat_ratio >>= 1;
34 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
35
36 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
37 gd->bus_clk / 16 / CONFIG_BAUDRATE);
38
39 puts("\nNAND boot... ");
40
41 /* copy code to RAM and jump to it - this should not return */
42 /* NOTE - code has to be copied out of NAND buffer before
43 * other blocks can be read.
44 */
45 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
46}
47
48void board_init_r(gd_t *gd, ulong dest_addr)
49{
50 puts("\nSecond program loader running in sram...");
51 nand_boot();
52}
53
54void putc(char c)
55{
56 if (c == '\n')
57 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
58
59 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
60}
61
62void puts(const char *str)
63{
64 while (*str)
65 putc(*str++);
66}