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git01.mediatek.com / filogic / uboot / 5b8577db0604e3b9e2ce61e86e6a1a2590cac537 / . / include / configs / hsdk-4xd.h
blob: f59da41773167e4f88e30fb213797d48c0d1e81e [file] [log] [blame]
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
5 */
6
7#ifndef _CONFIG_HSDK_H_
8#define _CONFIG_HSDK_H_
9
10#include <linux/sizes.h>
11
12/*
13 * CPU configuration
14 */
15#define NR_CPUS 4
16#define ARC_PERIPHERAL_BASE 0xF0000000
17#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
18#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
19
20/*
21 * Memory configuration
22 */
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]23
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]24#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
25#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]26#define CFG_SYS_SDRAM_SIZE SZ_1G
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]27
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]28/*
29 * UART configuration
30 */
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]31#define CFG_SYS_NS16550_CLK 33330000
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]32
33/*
34 * Ethernet PHY configuration
35 */
36
37/*
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]38 * Environment settings
39 */
Tom Rinic9edebe2022-12-04 10:03:50 -0500[diff] [blame]40#define CFG_EXTRA_ENV_SETTINGS \
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]41 "upgrade=if mmc rescan && " \
42 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
43 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
44 "\"Fail to upgrade.\n" \
45 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
46 "; fi\0" \
47 "core_mask=0xF\0" \
48 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
49setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
50setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
51setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
52 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
53setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
54setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
55setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
56 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
57setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
58setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
59setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
60 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
61setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
62setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
63setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
64 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
65setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
66setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
67setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
68 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
69 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
70setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
71setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
72setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
73setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
74 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
75 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
76setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
77setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
78setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
79setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
80setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
81 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
82 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
83setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
84setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
85setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
86setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
87setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
88setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
89
90/*
91 * Environment configuration
92 */
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]93
94/* Cli configuration */
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]95
96/*
97 * Callback configuration
98 */
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]99
100#endif /* _CONFIG_HSDK_H_ */