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git01.mediatek.com / filogic / uboot / 5b4ca3ed008896fbbc07add2c4a6c42e648a004d / . / board / ep82xxm / ep82xxm.c
blob: fdde5355b5dcf0fa23d1f7b15cf24d38819c3e6e [file] [log] [blame]
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]1/*
2 * Copyright (C) 2006 Embedded Planet, LLC.
3 *
4 * Support for Embedded Planet EP82xxM boards.
5 * Tested on EP82xxM (MPC8270).
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]8 */
9
10#include <common.h>
11#include <mpc8260.h>
12#include <ioports.h>
13#include <asm/m8260_pci.h>
14#ifdef CONFIG_PCI
15#include <pci.h>
16#endif
17#include <miiphy.h>
Wolfgang Denk41372ad2011-11-05 05:13:09 +0000[diff] [blame]18#include <linux/compiler.h>
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]19
20/*
21 * I/O Port configuration table
22 *
23 * if conf is 1, then that port pin will be configured at boot time
24 * according to the five values podr/pdir/ppar/psor/pdat for that entry
25 */
26
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]27#define CONFIG_SYS_FCC2 1
28#define CONFIG_SYS_FCC3 1
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]29
30const iop_conf_t iop_conf_tab[4][32] = {
31
32 /* Port A */
33 { /* conf ppar psor pdir podr pdat */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]34 /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
35 /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
36 /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
37 /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
38 /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
39 /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
40 /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
41 /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
42 /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
43 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
44 /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
45 /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
46 /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
47 /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
48 /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
49 /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
50 /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
51 /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
52 /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
53 /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
54 /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
55 /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
56 /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
57 /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
58 /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
59 /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
60 /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
61 /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
62 /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
63 /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
64 /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
65 /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]66 },
67
68 /* Port B */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]69 { /* conf ppar psor pdir podr pdat */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]70 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
71 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
72 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
73 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
74 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
75 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
76 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
77 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
78 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
79 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
80 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
81 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
82 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
83 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
84 /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
85 /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
86 /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
87 /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
88 /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
89 /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
90 /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
91 /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
92 /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
93 /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]94 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]95 /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
96 /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
97 /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]98 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
99 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
100 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
101 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]102 },
103
104 /* Port C */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]105 { /* conf ppar psor pdir podr pdat */
106 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
107 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
108 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
109 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]110 /* PC27 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]111 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
112 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
113 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
114 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
115 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
116 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
117 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]118 /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
119 /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
120 /* PC17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
121 /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]122 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
123 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
124 /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
125 /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
126 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
127 /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
128 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
129 /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
130 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
131 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
132 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
133 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
134 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
135 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
136 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
137 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]138 },
139
140 /* Port D */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]141 { /* conf ppar psor pdir podr pdat */
142 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
143 /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
144 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
145 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
146 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
147 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
148 /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
149 /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
150 /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
151 /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
152 /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
153 /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
154 /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
155 /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
156 /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
157 /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
158 /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
159 /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
160 /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
161 /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
162 /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
163 /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
164 /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
165 /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
166 /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
167 /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
168 /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
169 /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
170 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
171 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
172 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
173 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]174 }
175};
176
177#ifdef CONFIG_PCI
178typedef struct pci_ic_s {
179 unsigned long pci_int_stat;
180 unsigned long pci_int_mask;
181}pci_ic_t;
182#endif
183
184int board_early_init_f (void)
185{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]186 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]187
188 bcsr[4] |= 0x30; /* Turn the LEDs off */
189
190#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
191 bcsr[6] |= 0x10;
192#endif
193#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
194 bcsr[7] |= 0x10;
195#endif
196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]197#if CONFIG_SYS_FCC3
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]198 bcsr[8] |= 0xC0;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]199#endif /* CONFIG_SYS_FCC3 */
200#if CONFIG_SYS_FCC2
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]201 bcsr[8] |= 0x30;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]202#endif /* CONFIG_SYS_FCC2 */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]203
204 return 0;
205}
206
Becky Brucebd99ae72008-06-09 16:03:40 -0500[diff] [blame]207phys_size_t initdram(int board_type)
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]208{
209 /* Size in MB of SDRAM populated on board*/
210 long int msize = 256;
211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]212#ifndef CONFIG_SYS_RAMBOOT
213 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]214 volatile memctl8260_t *memctl = &immap->im_memctl;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]215 uint psdmr = CONFIG_SYS_PSDMR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]216 int i;
217
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]218 unsigned char *ramptr1 = (unsigned char *)0x00000110;
Wolfgang Denk41372ad2011-11-05 05:13:09 +0000[diff] [blame]219 __maybe_unused unsigned char ramtmp;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]220
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]221 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]222
223udelay(400);
224
225 /* Initialise 60x bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]226 memctl->memc_psrt = CONFIG_SYS_PSRT;
227 memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
228 memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]229 memctl->memc_psdmr = psdmr;
230
231udelay(400);
232
233 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
234 ramtmp = *ramptr1;
235 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
236 for (i = 0; i < 8; i++) {
237 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
238 }
239 ramtmp = *ramptr1;
240 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
241 *ramptr1 = 0xFF;
242 memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]243#endif /* !CONFIG_SYS_RAMBOOT */
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]244
245 /* Return total 60x bus SDRAM size */
246 return msize * 1024 * 1024;
247}
248
249int checkboard(void)
250{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]251 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
Wolfgang Denkb95ba802006-10-09 00:48:57 +0200[diff] [blame]252
253 puts("Board: ");
254 switch (bcsr[0]) {
255 case 0x0A:
256 printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
257 break;
258 default:
259 printf("unknown: ID=%02X\n", bcsr[0]);
260 }
261
262 return 0;
263}
264
265#ifdef CONFIG_PCI
266struct pci_controller hose;
267
268extern void pci_mpc8250_init(struct pci_controller *);
269
270void pci_init_board(void)
271{
272 pci_mpc8250_init(&hose);
273}
274#endif