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git01.mediatek.com / filogic / uboot / 5b1d713721c3ea02549940133f09236783dda1f9 / . / board / RPXlite / RPXlite.c
blob: a33357bc37160df29311bd145be25a9de9a4144d [file] [log] [blame]
wdenk5b1d7132002-11-03 00:07:02 +0000[diff] [blame^]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
26 * U-Boot port on RPXlite board
27 *
28 * DRAM related UPMA register values are modified.
29 * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
30 */
31
32#include <common.h>
33#include <mpc8xx.h>
34
35/* ------------------------------------------------------------------------- */
36
37static long int dram_size (long int, long int *, long int);
38
39/* ------------------------------------------------------------------------- */
40
41#define _NOT_USED_ 0xFFFFCC25
42
43const uint sdram_table[] =
44{
45 /*
46 * Single Read. (Offset 00h in UPMA RAM)
47 */
48 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
49 0x3FBFCC27, /* last */
50 _NOT_USED_, _NOT_USED_, _NOT_USED_,
51
52 /*
53 * Burst Read. (Offset 08h in UPMA RAM)
54 */
55 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
56 0x3FBFCC27, /* last */
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 _NOT_USED_, _NOT_USED_, _NOT_USED_,
60
61 /*
62 * Single Write. (Offset 18h in UPMA RAM)
63 */
64 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
65 0x3FFFCC27, /* last */
66 _NOT_USED_, _NOT_USED_, _NOT_USED_,
67
68 /*
69 * Burst Write. (Offset 20h in UPMA RAM)
70 */
71 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
72 0x0CFFCC00, 0x33FFCC27, /* last */
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 _NOT_USED_, _NOT_USED_,
76
77 /*
78 * Refresh. (Offset 30h in UPMA RAM)
79 */
80 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
81 0x3FFFCC27, /* last */
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 _NOT_USED_, _NOT_USED_, _NOT_USED_,
84
85 /*
86 * Exception. (Offset 3Ch in UPMA RAM)
87 */
88 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
89};
90
91/* ------------------------------------------------------------------------- */
92
93
94/*
95 * Check Board Identity:
96 */
97
98int checkboard (void)
99{
100 puts ("Board: RPXlite\n") ;
101 return (0) ;
102}
103
104/* ------------------------------------------------------------------------- */
105
106long int initdram (int board_type)
107{
108 volatile immap_t *immap = (immap_t *)CFG_IMMR;
109 volatile memctl8xx_t *memctl = &immap->im_memctl;
110 long int size10 ;
111
112 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
113
114 /* Refresh clock prescalar */
115 memctl->memc_mptpr = CFG_MPTPR ;
116
117 memctl->memc_mar = 0x00000000;
118
119 /* Map controller banks 1 to the SDRAM bank */
120 memctl->memc_or1 = CFG_OR1_PRELIM;
121 memctl->memc_br1 = CFG_BR1_PRELIM;
122
123 memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
124
125 udelay(200);
126
127 /* perform SDRAM initializsation sequence */
128
129 memctl->memc_mcr = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
130 udelay(1);
131
132 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
133
134 udelay (1000);
135
136 /* Check Bank 0 Memory Size
137 * try 10 column mode
138 */
139
140 size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
141
142 return (size10);
143}
144
145/* ------------------------------------------------------------------------- */
146
147/*
148 * Check memory range for valid RAM. A simple memory test determines
149 * the actually available RAM size between addresses `base' and
150 * `base + maxsize'. Some (not all) hardware errors are detected:
151 * - short between address lines
152 * - short between data lines
153 */
154
155static long int dram_size (long int mamr_value, long int *base, long int maxsize)
156{
157 volatile immap_t *immap = (immap_t *)CFG_IMMR;
158 volatile memctl8xx_t *memctl = &immap->im_memctl;
159 volatile long int *addr;
160 ulong cnt, val;
161 ulong save[32]; /* to make test non-destructive */
162 unsigned char i = 0;
163
164 memctl->memc_mamr = mamr_value;
165
166 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
167 addr = base + cnt; /* pointer arith! */
168
169 save[i++] = *addr;
170 *addr = ~cnt;
171 }
172
173 /* write 0 to base address */
174 addr = base;
175 save[i] = *addr;
176 *addr = 0;
177
178 /* check at base address */
179 if ((val = *addr) != 0) {
180 *addr = save[i];
181 return (0);
182 }
183
184 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
185 addr = base + cnt; /* pointer arith! */
186
187 val = *addr;
188 *addr = save[--i];
189
190 if (val != (~cnt)) {
191 return (cnt * sizeof(long));
192 }
193 }
194 return (maxsize);
195}