| Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 1 | /* |
| 2 | * clocks_am33xx.h |
| 3 | * |
| 4 | * AM33xx clock define |
| 5 | * |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 6 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 7 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef _CLOCKS_AM33XX_H_ |
| 12 | #define _CLOCKS_AM33XX_H_ |
| 13 | |
| Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame^] | 14 | /* MAIN PLL Fdll supported frequencies */ |
| 15 | #define MPUPLL_M_1000 1000 |
| 16 | #define MPUPLL_M_800 800 |
| 17 | #define MPUPLL_M_720 720 |
| 18 | #define MPUPLL_M_600 600 |
| 19 | #define MPUPLL_M_550 550 |
| 20 | #define MPUPLL_M_300 300 |
| 21 | |
| Mark Jackson | 52b003c | 2013-03-04 01:27:20 +0000 | [diff] [blame] | 22 | /* MAIN PLL Fdll = 550 MHz, by default */ |
| 23 | #ifndef CONFIG_SYS_MPUCLK |
| Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame^] | 24 | #define CONFIG_SYS_MPUCLK MPUPLL_M_550 |
| Mark Jackson | 52b003c | 2013-03-04 01:27:20 +0000 | [diff] [blame] | 25 | #endif |
| Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 26 | |
| Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 27 | #define UART_RESET (0x1 << 1) |
| 28 | #define UART_CLK_RUNNING_MASK 0x1 |
| 29 | #define UART_SMART_IDLE_EN (0x1 << 0x3) |
| 30 | |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 31 | extern void enable_dmm_clocks(void); |
| Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 32 | |
| 33 | #endif /* endif _CLOCKS_AM33XX_H_ */ |