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git01.mediatek.com / filogic / uboot / 5ac3486fc686625baae7e3bddac707636b041da6 / . / arch / arm / dts / synquacer-sc2a11-developerbox-u-boot.dtsi
blob: 9957646a466477f7f158b25fc0215267083e1791 [file] [log] [blame]
Masami Hiramatsuea0ab682021-06-04 18:44:59 +0900[diff] [blame]1// SPDX-License-Identifier: BSD-2-Clause-Patent
2//
3// Copyright (c) 2021, Linaro Limited. All rights reserved.
4//
5
6/ {
7 aliases {
8 spi_nor = &spi_nor;
9 i2c0 = &i2c0;
10 };
11
12 spi_nor: spi@54800000 {
13 compatible = "socionext,synquacer-spi";
14 reg = <0x00 0x54800000 0x00 0x1000>;
15 interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
16 clocks = <&clk_alw_1_8>;
17 clock-names = "iHCLK";
18 socionext,use-rtm;
19 socionext,set-aces;
20 #address-cells = <1>;
21 #size-cells = <0>;
22 status = "okay";
Masami Hiramatsuea0ab682021-06-04 18:44:59 +0900[diff] [blame]23
Jassi Brar790a9532023-05-31 00:29:32 -0500[diff] [blame]24 flash0: flash@0 {
Masami Hiramatsuea0ab682021-06-04 18:44:59 +0900[diff] [blame]25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
28 reg = <0>; /* Chip select 0 */
29 spi-max-frequency = <31250000>;
30 spi-rx-bus-width = <0x1>;
31 spi-tx-bus-width = <0x1>;
Masami Hiramatsuf0538e22021-07-12 19:36:03 +0900[diff] [blame]32
33 partitions {
34 compatible = "fixed-partitions";
35 #address-cells = <1>;
36 #size-cells = <1>;
37
38 partition@0 {
39 label = "BootStrap-BL1";
40 reg = <0x0 0x70000>;
41 read-only;
42 };
43
44 partition@70000 {
45 label = "Flash-Writer";
46 reg = <0x70000 0x90000>;
47 read-only;
48 };
49
50 partition@100000 {
51 label = "SCP-BL2";
52 reg = <0x100000 0x80000>;
53 read-only;
54 };
55
56 partition@180000 {
57 label = "FIP-TFA";
58 reg = <0x180000 0x78000>;
59 };
60
61 partition@1f8000 {
62 label = "Stage2Tables";
63 reg = <0x1f8000 0x8000>;
64 };
65
66 partition@200000 {
67 label = "U-Boot";
68 reg = <0x200000 0x100000>;
69 };
70
71 partition@300000 {
72 label = "UBoot-Env";
73 reg = <0x300000 0x100000>;
74 };
75
76 partition@500000 {
Jassi Brar790a9532023-05-31 00:29:32 -0500[diff] [blame]77 label = "MDATA-Pri";
78 reg = <0x500000 0x1000>;
79 };
80
81 partition@530000 {
82 label = "MDATA-Sec";
83 reg = <0x530000 0x1000>;
84 };
85
86 /* FWU Multi bank update partitions */
87 partition@600000 {
88 label = "FIP-Bank0";
89 reg = <0x600000 0x400000>;
90 };
91
92 partition@a00000 {
93 label = "FIP-Bank1";
94 reg = <0xa00000 0x400000>;
Masami Hiramatsuf0538e22021-07-12 19:36:03 +0900[diff] [blame]95 };
96 };
Masami Hiramatsuea0ab682021-06-04 18:44:59 +0900[diff] [blame]97 };
98 };
99
100 i2c0: i2c@51200000 {
101 compatible = "socionext,synquacer-i2c";
102 reg = <0x0 0x51200000 0x0 0x1000>;
103 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&clk_i2c>;
105 clock-names = "pclk";
106 clock-frequency = <400000>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 status = "okay";
110
111 pcf8563: rtc@51 {
112 compatible = "nxp,pcf8563";
113 reg = <0x51>;
114 };
115 };
116
117 firmware {
118 optee {
119 status = "okay";
120 };
Jassi Brar790a9532023-05-31 00:29:32 -0500[diff] [blame]121
122 fwu-mdata {
123 compatible = "u-boot,fwu-mdata-mtd";
124 fwu-mdata-store = <&flash0>;
125 mdata-parts = "MDATA-Pri", "MDATA-Sec";
126
127 fwu-bank0 {
128 id = <0>;
129 label = "FIP-Bank0";
130 fwu-image0 {
131 id = <0>;
132 offset = <0x0>;
133 size = <0x400000>;
134 uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
135 };
136 };
137 fwu-bank1 {
138 id = <1>;
139 label = "FIP-Bank1";
140 fwu-image0 {
141 id = <0>;
142 offset = <0x0>;
143 size = <0x400000>;
144 uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0";
145 };
146 };
147 };
Masami Hiramatsuea0ab682021-06-04 18:44:59 +0900[diff] [blame]148 };
149};
150
151&smmu {
152 status = "okay";
153};
154
155&pcie0 {
156 status = "okay";
157};
158
159&pcie1 {
160 status = "okay";
161};
162
163&sdhci {
164 status = "okay";
165};