| Dario Binacchi | da3b020 | 2020-12-30 00:06:32 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| 2 | # |
| 3 | # Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> |
| 4 | # |
| 5 | |
| Dario Binacchi | 6e6eb8b | 2020-12-30 00:06:34 +0100 | [diff] [blame] | 6 | config CLK_TI_AM3_DPLL |
| 7 | bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers" |
| 8 | depends on CLK && OF_CONTROL |
| 9 | help |
| 10 | This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL |
| 11 | provides all interface clocks and functional clocks to the processor. |
| 12 | |
| Dario Binacchi | d284157 | 2020-12-30 00:06:35 +0100 | [diff] [blame] | 13 | config CLK_TI_DIVIDER |
| 14 | bool "TI divider clock driver" |
| 15 | depends on CLK && OF_CONTROL && CLK_CCF |
| 16 | help |
| 17 | This enables the divider clock driver support on TI's SoCs. |
| 18 | |
| Dario Binacchi | b96e897 | 2020-12-30 00:06:36 +0100 | [diff] [blame] | 19 | config CLK_TI_GATE |
| 20 | bool "TI gate clock driver" |
| 21 | depends on CLK && OF_CONTROL |
| 22 | help |
| 23 | This enables the gate clock driver support on TI's SoCs. |
| 24 | |
| Dario Binacchi | da3b020 | 2020-12-30 00:06:32 +0100 | [diff] [blame] | 25 | config CLK_TI_MUX |
| 26 | bool "TI mux clock driver" |
| 27 | depends on CLK && OF_CONTROL && CLK_CCF |
| 28 | help |
| 29 | This enables the mux clock driver support on TI's SoCs. |