Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 8 | #include <clk-uclass.h> |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 9 | #include <dm/device.h> |
| 10 | |
| 11 | DECLARE_GLOBAL_DATA_PTR; |
| 12 | |
| 13 | struct clk_fixed_rate { |
| 14 | unsigned long fixed_rate; |
| 15 | }; |
| 16 | |
| 17 | #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) |
| 18 | |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 19 | static ulong clk_fixed_rate_get_rate(struct clk *clk) |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 20 | { |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 21 | if (clk->id != 0) |
| 22 | return -EINVAL; |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 23 | |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 24 | return to_clk_fixed_rate(clk->dev)->fixed_rate; |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 25 | } |
| 26 | |
| 27 | const struct clk_ops clk_fixed_rate_ops = { |
| 28 | .get_rate = clk_fixed_rate_get_rate, |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) |
| 32 | { |
Simon Glass | 589d915 | 2016-07-04 11:58:03 -0600 | [diff] [blame^] | 33 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 34 | to_clk_fixed_rate(dev)->fixed_rate = |
| 35 | fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
| 36 | "clock-frequency", 0); |
Simon Glass | 589d915 | 2016-07-04 11:58:03 -0600 | [diff] [blame^] | 37 | #endif |
Masahiro Yamada | 31adfc2 | 2016-01-19 13:55:28 +0900 | [diff] [blame] | 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | static const struct udevice_id clk_fixed_rate_match[] = { |
| 43 | { |
| 44 | .compatible = "fixed-clock", |
| 45 | }, |
| 46 | { /* sentinel */ } |
| 47 | }; |
| 48 | |
| 49 | U_BOOT_DRIVER(clk_fixed_rate) = { |
| 50 | .name = "fixed_rate_clock", |
| 51 | .id = UCLASS_CLK, |
| 52 | .of_match = clk_fixed_rate_match, |
| 53 | .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata, |
| 54 | .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate), |
| 55 | .ops = &clk_fixed_rate_ops, |
| 56 | }; |