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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass45be32c2014-12-10 08:55:51 -07002/*
3 * Test-related constants for sandbox
4 *
5 * Copyright (c) 2014 Google, Inc
Simon Glass45be32c2014-12-10 08:55:51 -07006 */
7
8#ifndef __ASM_TEST_H
9#define __ASM_TEST_H
10
Simon Glassc3b5adf2021-11-19 13:23:50 -070011#include <video.h>
Pali Rohár417ae2c2022-02-18 13:16:18 +010012#include <pci_ids.h>
Simon Glassc3b5adf2021-11-19 13:23:50 -070013
Simon Glass45be32c2014-12-10 08:55:51 -070014/* The sandbox driver always permits an I2C device with this address */
Simon Glass70778bc2015-03-05 12:25:26 -070015#define SANDBOX_I2C_TEST_ADDR 0x59
16
17#define SANDBOX_PCI_VENDOR_ID 0x1234
Simon Glass21c8f1a2019-09-25 08:56:01 -060018#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
Simon Glass8c501022019-12-06 21:41:54 -070019#define SANDBOX_PCI_PMC_EMUL_ID 0x5677
Simon Glass937bb472019-12-06 21:41:57 -070020#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
Pali Rohár417ae2c2022-02-18 13:16:18 +010021#define SANDBOX_PCI_CLASS_CODE (PCI_CLASS_COMMUNICATION_SERIAL >> 8)
22#define SANDBOX_PCI_CLASS_SUB_CODE (PCI_CLASS_COMMUNICATION_SERIAL & 0xff)
Simon Glass45be32c2014-12-10 08:55:51 -070023
Bin Mengd74d3122018-08-03 01:14:53 -070024#define PCI_CAP_ID_PM_OFFSET 0x50
25#define PCI_CAP_ID_EXP_OFFSET 0x60
26#define PCI_CAP_ID_MSIX_OFFSET 0x70
Alex Margineanf1274432019-06-07 11:24:24 +030027#define PCI_CAP_ID_EA_OFFSET 0x80
Bin Mengd74d3122018-08-03 01:14:53 -070028
29#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
30#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
31#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
32
Bin Mengc69ae412018-08-03 01:14:46 -070033/* Useful for PCI_VDEVICE() macro */
34#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
35#define SWAP_CASE_DRV_DATA 0x55aa
36
Simon Glass8cc4d822015-07-06 12:54:24 -060037#define SANDBOX_CLK_RATE 32768
38
Alex Margineanf1274432019-06-07 11:24:24 +030039/* Macros used to test PCI EA capability structure */
40#define PCI_CAP_EA_BASE_LO0 0x00100000
41#define PCI_CAP_EA_BASE_LO1 0x00110000
42#define PCI_CAP_EA_BASE_LO2 0x00120000
43#define PCI_CAP_EA_BASE_LO4 0x00140000
44#define PCI_CAP_EA_BASE_HI2 0x00020000ULL
45#define PCI_CAP_EA_BASE_HI4 0x00040000ULL
46#define PCI_CAP_EA_SIZE_LO 0x0000ffff
47#define PCI_CAP_EA_SIZE_HI 0x00000010ULL
48#define PCI_EA_BAR2_MAGIC 0x72727272
49#define PCI_EA_BAR4_MAGIC 0x74747474
50
Simon Glassa847b272020-02-06 09:54:57 -070051enum {
52 SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */
53};
54
Simon Glasscd556522015-07-06 12:54:35 -060055/* System controller driver data */
56enum {
57 SYSCON0 = 32,
58 SYSCON1,
59
60 SYSCON_COUNT
61};
62
Simon Glass4c70ed92015-04-20 12:37:15 -060063/**
Simon Glass9b306e52021-01-16 14:52:22 -070064 */
65enum cros_ec_test_t {
66 CROSECT_BREAK_HELLO = BIT(1),
Simon Glass9d702522021-01-16 14:52:28 -070067 CROSECT_LID_OPEN = BIT(2),
Simon Glass9b306e52021-01-16 14:52:22 -070068};
69
70/**
Simon Glass4c70ed92015-04-20 12:37:15 -060071 * sandbox_i2c_set_test_mode() - set test mode for running unit tests
72 *
73 * See sandbox_i2c_xfer() for the behaviour changes.
74 *
75 * @bus: sandbox I2C bus to adjust
76 * @test_mode: true to select test mode, false to run normally
77 */
78void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
79
Simon Glass45be32c2014-12-10 08:55:51 -070080enum sandbox_i2c_eeprom_test_mode {
81 SIE_TEST_MODE_NONE,
82 /* Permits read/write of only one byte per I2C transaction */
83 SIE_TEST_MODE_SINGLE_BYTE,
84};
85
86void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
87 enum sandbox_i2c_eeprom_test_mode mode);
88
89void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
90
Robert Beckettf695f6e2019-10-28 17:44:59 +000091void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev,
92 uint mask);
93
Robert Beckett1fe8a492019-10-28 17:44:58 +000094uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev);
95
96uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev);
97
Simon Glassc404aa62015-04-20 12:37:24 -060098/**
99 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
100 *
101 * @dev: RTC device to adjust
102 * @use_system_time: true to use system time, false to use @base_time
103 * @offset: RTC offset from current system/base time (-1 for no
104 * change)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100105 * Return: old value of RTC offset
Simon Glassc404aa62015-04-20 12:37:24 -0600106 */
107long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
108 int offset);
109
110/**
111 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
112 *
113 * @dev: RTC device to adjust
114 * @base_time: New base system time (set to -1 for no change)
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100115 * Return: old base time
Simon Glassc404aa62015-04-20 12:37:24 -0600116 */
117long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
118
Simon Glassbe4ebd12015-11-08 23:48:06 -0700119int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
120
Mario Six02ad6fb2018-09-27 09:19:31 +0200121/**
122 * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
123 *
124 * @dev: OSD device for which to access the internal memory for
125 * @buf: pointer to buffer to receive the OSD memory data
126 * @buflen: length of buffer in bytes
127 */
128int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
Simon Glass5620cf82018-10-01 12:22:40 -0600129
130/**
131 * sandbox_pwm_get_config() - get the PWM config for a channel
132 *
133 * @dev: Device to check
134 * @channel: Channel number to check
135 * @period_ns: Period of the PWM in nanoseconds
136 * @duty_ns: Current duty cycle of the PWM in nanoseconds
137 * @enable: true if the PWM is enabled
138 * @polarity: true if the PWM polarity is active high
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100139 * Return: 0 if OK, -ENOSPC if the PWM number is invalid
Simon Glass5620cf82018-10-01 12:22:40 -0600140 */
141int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp,
142 uint *duty_nsp, bool *enablep, bool *polarityp);
143
Simon Glass36eee8c2018-11-06 15:21:41 -0700144/**
145 * sandbox_sf_set_block_protect() - Set the BP bits of the status register
146 *
147 * @dev: Device to update
148 * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7)
149 */
150void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask);
151
Simon Glassed96cde2018-12-10 10:37:33 -0700152/**
153 * sandbox_get_codec_params() - Read back codec parameters
154 *
155 * This reads back the parameters set by audio_codec_set_params() for the
156 * sandbox audio driver. Arguments are as for that function.
157 */
158void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
159 int *mclk_freqp, int *bits_per_samplep,
160 uint *channelsp);
161
Simon Glassc953aaf2018-12-10 10:37:34 -0700162/**
163 * sandbox_get_i2s_sum() - Read back the sum of the audio data so far
164 *
165 * This data is provided to the sandbox driver by the I2S tx_data() method.
166 *
167 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100168 * Return: sum of audio data
Simon Glassc953aaf2018-12-10 10:37:34 -0700169 */
170int sandbox_get_i2s_sum(struct udevice *dev);
171
Simon Glass76072ac2018-12-10 10:37:36 -0700172/**
173 * sandbox_get_setup_called() - Returns the number of times setup(*) was called
174 *
175 * This is used in the sound test
176 *
177 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100178 * Return: call count for the setup() method
Simon Glass76072ac2018-12-10 10:37:36 -0700179 */
180int sandbox_get_setup_called(struct udevice *dev);
181
182/**
Simon Glass70bc14b2020-02-03 07:36:06 -0700183 * sandbox_get_sound_active() - Returns whether sound play is in progress
184 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100185 * Return: true if active, false if not
Simon Glass70bc14b2020-02-03 07:36:06 -0700186 */
187int sandbox_get_sound_active(struct udevice *dev);
188
189/**
Simon Glass76072ac2018-12-10 10:37:36 -0700190 * sandbox_get_sound_sum() - Read back the sum of the sound data so far
191 *
192 * This data is provided to the sandbox driver by the sound play() method.
193 *
194 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100195 * Return: sum of audio data
Simon Glass76072ac2018-12-10 10:37:36 -0700196 */
197int sandbox_get_sound_sum(struct udevice *dev);
198
Simon Glass53a68b32019-02-16 20:24:50 -0700199/**
Simon Glassecd02e72019-02-16 20:24:54 -0700200 * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
201 *
202 * @dev: Device to update
203 * @allow: true to allow the start_beep() method, false to disallow it
204 */
205void sandbox_set_allow_beep(struct udevice *dev, bool allow);
206
207/**
208 * sandbox_get_beep_frequency() - Get the frequency of the current beep
209 *
210 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100211 * Return: frequency of beep, if there is an active beep, else 0
Simon Glassecd02e72019-02-16 20:24:54 -0700212 */
213int sandbox_get_beep_frequency(struct udevice *dev);
214
215/**
Ovidiu Panaita2c9d012020-12-14 19:06:49 +0200216 * sandbox_spi_get_speed() - Get current speed setting of a sandbox spi bus
217 *
218 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100219 * Return: current bus speed
Ovidiu Panaita2c9d012020-12-14 19:06:49 +0200220 */
221uint sandbox_spi_get_speed(struct udevice *dev);
222
223/**
224 * sandbox_spi_get_mode() - Get current mode setting of a sandbox spi bus
225 *
226 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100227 * Return: current mode
Ovidiu Panaita2c9d012020-12-14 19:06:49 +0200228 */
229uint sandbox_spi_get_mode(struct udevice *dev);
230
231/**
Simon Glass53a68b32019-02-16 20:24:50 -0700232 * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
233 *
234 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100235 * Return: 0 if not protected, 1 if protected
Simon Glass53a68b32019-02-16 20:24:50 -0700236 */
237int sandbox_get_pch_spi_protect(struct udevice *dev);
238
Ramon Friedafdb3422019-04-27 11:15:24 +0300239/**
240 * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
241 *
242 * @dev: Device to check
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100243 * Return: irq count
Ramon Friedafdb3422019-04-27 11:15:24 +0300244 */
245int sandbox_get_pci_ep_irq_count(struct udevice *dev);
246
Simon Glass72231f72019-09-25 08:56:42 -0600247/**
248 * sandbox_pci_read_bar() - Read the BAR value for a read_config operation
249 *
250 * This is used in PCI emulators to read a base address reset. This has special
251 * rules because when the register is set to 0xffffffff it can be used to
252 * discover the type and size of the BAR.
253 *
254 * @barval: Current value of the BAR
255 * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or
256 * PCI_BASE_ADDRESS_MEM_TYPE_32)
257 * @size: Size of BAR in bytes
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100258 * Return: BAR value to return from emulator
Simon Glass72231f72019-09-25 08:56:42 -0600259 */
260uint sandbox_pci_read_bar(u32 barval, int type, uint size);
261
Simon Glassc667fb02019-10-11 16:16:48 -0600262/**
263 * sandbox_set_enable_memio() - Enable readl/writel() for sandbox
264 *
265 * Normally these I/O functions do nothing with sandbox. Certain tests need them
266 * to work as for other architectures, so this function can be used to enable
267 * them.
268 *
269 * @enable: true to enable, false to disable
270 */
271void sandbox_set_enable_memio(bool enable);
272
Simon Glass9b306e52021-01-16 14:52:22 -0700273/**
274 * sandbox_cros_ec_set_test_flags() - Set behaviour for testing purposes
275 *
276 * @dev: Device to check
277 * @flags: Flags to control behaviour (CROSECT_...)
278 */
279void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags);
280
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300281/**
282 * sandbox_cros_ec_get_pwm_duty() - Get EC PWM config for testing purposes
283 *
284 * @dev: Device to check
285 * @index: PWM channel index
286 * @duty: Current duty cycle in 0..EC_PWM_MAX_DUTY range.
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100287 * Return: 0 if OK, -ENOSPC if the PWM number is invalid
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300288 */
289int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty);
290
Simon Glassc3b5adf2021-11-19 13:23:50 -0700291/**
292 * sandbox_sdl_set_bpp() - Set the depth of the sandbox display
293 *
294 * The device must not be active when this function is called. It activiates it
295 * before returning.
296 *
297 * This updates the depth value and adjusts a few other settings accordingly.
298 * It must be called before the display is probed.
299 *
300 * @dev: Device to adjust
301 * @l2bpp: depth to set
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100302 * Return: 0 if the device was already active, other error if it fails to probe
Simon Glassc3b5adf2021-11-19 13:23:50 -0700303 * after the change
304 */
305int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp);
306
Simon Glass161e1e32022-07-30 15:52:22 -0600307/**
308 * sandbox_set_fake_efi_mgr_dev() - Control EFI bootmgr producing valid bootflow
309 *
310 * This is only used for testing.
311 *
312 * @dev: efi_mgr bootmeth device
313 * @fake_dev: true to produce a valid bootflow when requested, false to produce
314 * an error
315 */
316void sandbox_set_fake_efi_mgr_dev(struct udevice *dev, bool fake_dev);
317
Simon Glass45be32c2014-12-10 08:55:51 -0700318#endif