Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Simon Glass | 45be32c | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Test-related constants for sandbox |
| 4 | * |
| 5 | * Copyright (c) 2014 Google, Inc |
Simon Glass | 45be32c | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_TEST_H |
| 9 | #define __ASM_TEST_H |
| 10 | |
Simon Glass | c3b5adf | 2021-11-19 13:23:50 -0700 | [diff] [blame] | 11 | #include <video.h> |
Pali Rohár | 417ae2c | 2022-02-18 13:16:18 +0100 | [diff] [blame] | 12 | #include <pci_ids.h> |
Simon Glass | c3b5adf | 2021-11-19 13:23:50 -0700 | [diff] [blame] | 13 | |
Simon Glass | 45be32c | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 14 | /* The sandbox driver always permits an I2C device with this address */ |
Simon Glass | 70778bc | 2015-03-05 12:25:26 -0700 | [diff] [blame] | 15 | #define SANDBOX_I2C_TEST_ADDR 0x59 |
| 16 | |
| 17 | #define SANDBOX_PCI_VENDOR_ID 0x1234 |
Simon Glass | 21c8f1a | 2019-09-25 08:56:01 -0600 | [diff] [blame] | 18 | #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 |
Simon Glass | 8c50102 | 2019-12-06 21:41:54 -0700 | [diff] [blame] | 19 | #define SANDBOX_PCI_PMC_EMUL_ID 0x5677 |
Simon Glass | 937bb47 | 2019-12-06 21:41:57 -0700 | [diff] [blame] | 20 | #define SANDBOX_PCI_P2SB_EMUL_ID 0x5676 |
Pali Rohár | 417ae2c | 2022-02-18 13:16:18 +0100 | [diff] [blame] | 21 | #define SANDBOX_PCI_CLASS_CODE (PCI_CLASS_COMMUNICATION_SERIAL >> 8) |
| 22 | #define SANDBOX_PCI_CLASS_SUB_CODE (PCI_CLASS_COMMUNICATION_SERIAL & 0xff) |
Simon Glass | 45be32c | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 23 | |
Bin Meng | d74d312 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 24 | #define PCI_CAP_ID_PM_OFFSET 0x50 |
| 25 | #define PCI_CAP_ID_EXP_OFFSET 0x60 |
| 26 | #define PCI_CAP_ID_MSIX_OFFSET 0x70 |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 27 | #define PCI_CAP_ID_EA_OFFSET 0x80 |
Bin Meng | d74d312 | 2018-08-03 01:14:53 -0700 | [diff] [blame] | 28 | |
| 29 | #define PCI_EXT_CAP_ID_ERR_OFFSET 0x100 |
| 30 | #define PCI_EXT_CAP_ID_VC_OFFSET 0x200 |
| 31 | #define PCI_EXT_CAP_ID_DSN_OFFSET 0x300 |
| 32 | |
Bin Meng | c69ae41 | 2018-08-03 01:14:46 -0700 | [diff] [blame] | 33 | /* Useful for PCI_VDEVICE() macro */ |
| 34 | #define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID |
| 35 | #define SWAP_CASE_DRV_DATA 0x55aa |
| 36 | |
Simon Glass | 8cc4d82 | 2015-07-06 12:54:24 -0600 | [diff] [blame] | 37 | #define SANDBOX_CLK_RATE 32768 |
| 38 | |
Alex Marginean | f127443 | 2019-06-07 11:24:24 +0300 | [diff] [blame] | 39 | /* Macros used to test PCI EA capability structure */ |
| 40 | #define PCI_CAP_EA_BASE_LO0 0x00100000 |
| 41 | #define PCI_CAP_EA_BASE_LO1 0x00110000 |
| 42 | #define PCI_CAP_EA_BASE_LO2 0x00120000 |
| 43 | #define PCI_CAP_EA_BASE_LO4 0x00140000 |
| 44 | #define PCI_CAP_EA_BASE_HI2 0x00020000ULL |
| 45 | #define PCI_CAP_EA_BASE_HI4 0x00040000ULL |
| 46 | #define PCI_CAP_EA_SIZE_LO 0x0000ffff |
| 47 | #define PCI_CAP_EA_SIZE_HI 0x00000010ULL |
| 48 | #define PCI_EA_BAR2_MAGIC 0x72727272 |
| 49 | #define PCI_EA_BAR4_MAGIC 0x74747474 |
| 50 | |
Simon Glass | a847b27 | 2020-02-06 09:54:57 -0700 | [diff] [blame] | 51 | enum { |
| 52 | SANDBOX_IRQN_PEND = 1, /* Interrupt number for 'pending' test */ |
| 53 | }; |
| 54 | |
Simon Glass | cd55652 | 2015-07-06 12:54:35 -0600 | [diff] [blame] | 55 | /* System controller driver data */ |
| 56 | enum { |
| 57 | SYSCON0 = 32, |
| 58 | SYSCON1, |
| 59 | |
| 60 | SYSCON_COUNT |
| 61 | }; |
| 62 | |
Simon Glass | 4c70ed9 | 2015-04-20 12:37:15 -0600 | [diff] [blame] | 63 | /** |
Simon Glass | 9b306e5 | 2021-01-16 14:52:22 -0700 | [diff] [blame] | 64 | */ |
| 65 | enum cros_ec_test_t { |
| 66 | CROSECT_BREAK_HELLO = BIT(1), |
Simon Glass | 9d70252 | 2021-01-16 14:52:28 -0700 | [diff] [blame] | 67 | CROSECT_LID_OPEN = BIT(2), |
Simon Glass | 9b306e5 | 2021-01-16 14:52:22 -0700 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | /** |
Simon Glass | 4c70ed9 | 2015-04-20 12:37:15 -0600 | [diff] [blame] | 71 | * sandbox_i2c_set_test_mode() - set test mode for running unit tests |
| 72 | * |
| 73 | * See sandbox_i2c_xfer() for the behaviour changes. |
| 74 | * |
| 75 | * @bus: sandbox I2C bus to adjust |
| 76 | * @test_mode: true to select test mode, false to run normally |
| 77 | */ |
| 78 | void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode); |
| 79 | |
Simon Glass | 45be32c | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 80 | enum sandbox_i2c_eeprom_test_mode { |
| 81 | SIE_TEST_MODE_NONE, |
| 82 | /* Permits read/write of only one byte per I2C transaction */ |
| 83 | SIE_TEST_MODE_SINGLE_BYTE, |
| 84 | }; |
| 85 | |
| 86 | void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, |
| 87 | enum sandbox_i2c_eeprom_test_mode mode); |
| 88 | |
| 89 | void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len); |
| 90 | |
Robert Beckett | f695f6e | 2019-10-28 17:44:59 +0000 | [diff] [blame] | 91 | void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev, |
| 92 | uint mask); |
| 93 | |
Robert Beckett | 1fe8a49 | 2019-10-28 17:44:58 +0000 | [diff] [blame] | 94 | uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev); |
| 95 | |
| 96 | uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev); |
| 97 | |
Simon Glass | c404aa6 | 2015-04-20 12:37:24 -0600 | [diff] [blame] | 98 | /** |
| 99 | * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time |
| 100 | * |
| 101 | * @dev: RTC device to adjust |
| 102 | * @use_system_time: true to use system time, false to use @base_time |
| 103 | * @offset: RTC offset from current system/base time (-1 for no |
| 104 | * change) |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 105 | * Return: old value of RTC offset |
Simon Glass | c404aa6 | 2015-04-20 12:37:24 -0600 | [diff] [blame] | 106 | */ |
| 107 | long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time, |
| 108 | int offset); |
| 109 | |
| 110 | /** |
| 111 | * sandbox_i2c_rtc_get_set_base_time() - get and set the base time |
| 112 | * |
| 113 | * @dev: RTC device to adjust |
| 114 | * @base_time: New base system time (set to -1 for no change) |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 115 | * Return: old base time |
Simon Glass | c404aa6 | 2015-04-20 12:37:24 -0600 | [diff] [blame] | 116 | */ |
| 117 | long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time); |
| 118 | |
Simon Glass | be4ebd1 | 2015-11-08 23:48:06 -0700 | [diff] [blame] | 119 | int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str); |
| 120 | |
Mario Six | 02ad6fb | 2018-09-27 09:19:31 +0200 | [diff] [blame] | 121 | /** |
| 122 | * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD |
| 123 | * |
| 124 | * @dev: OSD device for which to access the internal memory for |
| 125 | * @buf: pointer to buffer to receive the OSD memory data |
| 126 | * @buflen: length of buffer in bytes |
| 127 | */ |
| 128 | int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen); |
Simon Glass | 5620cf8 | 2018-10-01 12:22:40 -0600 | [diff] [blame] | 129 | |
| 130 | /** |
| 131 | * sandbox_pwm_get_config() - get the PWM config for a channel |
| 132 | * |
| 133 | * @dev: Device to check |
| 134 | * @channel: Channel number to check |
| 135 | * @period_ns: Period of the PWM in nanoseconds |
| 136 | * @duty_ns: Current duty cycle of the PWM in nanoseconds |
| 137 | * @enable: true if the PWM is enabled |
| 138 | * @polarity: true if the PWM polarity is active high |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 139 | * Return: 0 if OK, -ENOSPC if the PWM number is invalid |
Simon Glass | 5620cf8 | 2018-10-01 12:22:40 -0600 | [diff] [blame] | 140 | */ |
| 141 | int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp, |
| 142 | uint *duty_nsp, bool *enablep, bool *polarityp); |
| 143 | |
Simon Glass | 36eee8c | 2018-11-06 15:21:41 -0700 | [diff] [blame] | 144 | /** |
| 145 | * sandbox_sf_set_block_protect() - Set the BP bits of the status register |
| 146 | * |
| 147 | * @dev: Device to update |
| 148 | * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7) |
| 149 | */ |
| 150 | void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask); |
| 151 | |
Simon Glass | ed96cde | 2018-12-10 10:37:33 -0700 | [diff] [blame] | 152 | /** |
| 153 | * sandbox_get_codec_params() - Read back codec parameters |
| 154 | * |
| 155 | * This reads back the parameters set by audio_codec_set_params() for the |
| 156 | * sandbox audio driver. Arguments are as for that function. |
| 157 | */ |
| 158 | void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep, |
| 159 | int *mclk_freqp, int *bits_per_samplep, |
| 160 | uint *channelsp); |
| 161 | |
Simon Glass | c953aaf | 2018-12-10 10:37:34 -0700 | [diff] [blame] | 162 | /** |
| 163 | * sandbox_get_i2s_sum() - Read back the sum of the audio data so far |
| 164 | * |
| 165 | * This data is provided to the sandbox driver by the I2S tx_data() method. |
| 166 | * |
| 167 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 168 | * Return: sum of audio data |
Simon Glass | c953aaf | 2018-12-10 10:37:34 -0700 | [diff] [blame] | 169 | */ |
| 170 | int sandbox_get_i2s_sum(struct udevice *dev); |
| 171 | |
Simon Glass | 76072ac | 2018-12-10 10:37:36 -0700 | [diff] [blame] | 172 | /** |
| 173 | * sandbox_get_setup_called() - Returns the number of times setup(*) was called |
| 174 | * |
| 175 | * This is used in the sound test |
| 176 | * |
| 177 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 178 | * Return: call count for the setup() method |
Simon Glass | 76072ac | 2018-12-10 10:37:36 -0700 | [diff] [blame] | 179 | */ |
| 180 | int sandbox_get_setup_called(struct udevice *dev); |
| 181 | |
| 182 | /** |
Simon Glass | 70bc14b | 2020-02-03 07:36:06 -0700 | [diff] [blame] | 183 | * sandbox_get_sound_active() - Returns whether sound play is in progress |
| 184 | * |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 185 | * Return: true if active, false if not |
Simon Glass | 70bc14b | 2020-02-03 07:36:06 -0700 | [diff] [blame] | 186 | */ |
| 187 | int sandbox_get_sound_active(struct udevice *dev); |
| 188 | |
| 189 | /** |
Simon Glass | 76072ac | 2018-12-10 10:37:36 -0700 | [diff] [blame] | 190 | * sandbox_get_sound_sum() - Read back the sum of the sound data so far |
| 191 | * |
| 192 | * This data is provided to the sandbox driver by the sound play() method. |
| 193 | * |
| 194 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 195 | * Return: sum of audio data |
Simon Glass | 76072ac | 2018-12-10 10:37:36 -0700 | [diff] [blame] | 196 | */ |
| 197 | int sandbox_get_sound_sum(struct udevice *dev); |
| 198 | |
Simon Glass | 53a68b3 | 2019-02-16 20:24:50 -0700 | [diff] [blame] | 199 | /** |
Simon Glass | ecd02e7 | 2019-02-16 20:24:54 -0700 | [diff] [blame] | 200 | * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported |
| 201 | * |
| 202 | * @dev: Device to update |
| 203 | * @allow: true to allow the start_beep() method, false to disallow it |
| 204 | */ |
| 205 | void sandbox_set_allow_beep(struct udevice *dev, bool allow); |
| 206 | |
| 207 | /** |
| 208 | * sandbox_get_beep_frequency() - Get the frequency of the current beep |
| 209 | * |
| 210 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 211 | * Return: frequency of beep, if there is an active beep, else 0 |
Simon Glass | ecd02e7 | 2019-02-16 20:24:54 -0700 | [diff] [blame] | 212 | */ |
| 213 | int sandbox_get_beep_frequency(struct udevice *dev); |
| 214 | |
| 215 | /** |
Ovidiu Panait | a2c9d01 | 2020-12-14 19:06:49 +0200 | [diff] [blame] | 216 | * sandbox_spi_get_speed() - Get current speed setting of a sandbox spi bus |
| 217 | * |
| 218 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 219 | * Return: current bus speed |
Ovidiu Panait | a2c9d01 | 2020-12-14 19:06:49 +0200 | [diff] [blame] | 220 | */ |
| 221 | uint sandbox_spi_get_speed(struct udevice *dev); |
| 222 | |
| 223 | /** |
| 224 | * sandbox_spi_get_mode() - Get current mode setting of a sandbox spi bus |
| 225 | * |
| 226 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 227 | * Return: current mode |
Ovidiu Panait | a2c9d01 | 2020-12-14 19:06:49 +0200 | [diff] [blame] | 228 | */ |
| 229 | uint sandbox_spi_get_mode(struct udevice *dev); |
| 230 | |
| 231 | /** |
Simon Glass | 53a68b3 | 2019-02-16 20:24:50 -0700 | [diff] [blame] | 232 | * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status |
| 233 | * |
| 234 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 235 | * Return: 0 if not protected, 1 if protected |
Simon Glass | 53a68b3 | 2019-02-16 20:24:50 -0700 | [diff] [blame] | 236 | */ |
| 237 | int sandbox_get_pch_spi_protect(struct udevice *dev); |
| 238 | |
Ramon Fried | afdb342 | 2019-04-27 11:15:24 +0300 | [diff] [blame] | 239 | /** |
| 240 | * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count |
| 241 | * |
| 242 | * @dev: Device to check |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 243 | * Return: irq count |
Ramon Fried | afdb342 | 2019-04-27 11:15:24 +0300 | [diff] [blame] | 244 | */ |
| 245 | int sandbox_get_pci_ep_irq_count(struct udevice *dev); |
| 246 | |
Simon Glass | 72231f7 | 2019-09-25 08:56:42 -0600 | [diff] [blame] | 247 | /** |
| 248 | * sandbox_pci_read_bar() - Read the BAR value for a read_config operation |
| 249 | * |
| 250 | * This is used in PCI emulators to read a base address reset. This has special |
| 251 | * rules because when the register is set to 0xffffffff it can be used to |
| 252 | * discover the type and size of the BAR. |
| 253 | * |
| 254 | * @barval: Current value of the BAR |
| 255 | * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or |
| 256 | * PCI_BASE_ADDRESS_MEM_TYPE_32) |
| 257 | * @size: Size of BAR in bytes |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 258 | * Return: BAR value to return from emulator |
Simon Glass | 72231f7 | 2019-09-25 08:56:42 -0600 | [diff] [blame] | 259 | */ |
| 260 | uint sandbox_pci_read_bar(u32 barval, int type, uint size); |
| 261 | |
Simon Glass | c667fb0 | 2019-10-11 16:16:48 -0600 | [diff] [blame] | 262 | /** |
| 263 | * sandbox_set_enable_memio() - Enable readl/writel() for sandbox |
| 264 | * |
| 265 | * Normally these I/O functions do nothing with sandbox. Certain tests need them |
| 266 | * to work as for other architectures, so this function can be used to enable |
| 267 | * them. |
| 268 | * |
| 269 | * @enable: true to enable, false to disable |
| 270 | */ |
| 271 | void sandbox_set_enable_memio(bool enable); |
| 272 | |
Simon Glass | 9b306e5 | 2021-01-16 14:52:22 -0700 | [diff] [blame] | 273 | /** |
| 274 | * sandbox_cros_ec_set_test_flags() - Set behaviour for testing purposes |
| 275 | * |
| 276 | * @dev: Device to check |
| 277 | * @flags: Flags to control behaviour (CROSECT_...) |
| 278 | */ |
| 279 | void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags); |
| 280 | |
Alper Nebi Yasak | 8a8cd4f | 2021-05-19 19:33:31 +0300 | [diff] [blame] | 281 | /** |
| 282 | * sandbox_cros_ec_get_pwm_duty() - Get EC PWM config for testing purposes |
| 283 | * |
| 284 | * @dev: Device to check |
| 285 | * @index: PWM channel index |
| 286 | * @duty: Current duty cycle in 0..EC_PWM_MAX_DUTY range. |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 287 | * Return: 0 if OK, -ENOSPC if the PWM number is invalid |
Alper Nebi Yasak | 8a8cd4f | 2021-05-19 19:33:31 +0300 | [diff] [blame] | 288 | */ |
| 289 | int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty); |
| 290 | |
Simon Glass | c3b5adf | 2021-11-19 13:23:50 -0700 | [diff] [blame] | 291 | /** |
| 292 | * sandbox_sdl_set_bpp() - Set the depth of the sandbox display |
| 293 | * |
| 294 | * The device must not be active when this function is called. It activiates it |
| 295 | * before returning. |
| 296 | * |
| 297 | * This updates the depth value and adjusts a few other settings accordingly. |
| 298 | * It must be called before the display is probed. |
| 299 | * |
| 300 | * @dev: Device to adjust |
| 301 | * @l2bpp: depth to set |
Heinrich Schuchardt | 47b4c02 | 2022-01-19 18:05:50 +0100 | [diff] [blame] | 302 | * Return: 0 if the device was already active, other error if it fails to probe |
Simon Glass | c3b5adf | 2021-11-19 13:23:50 -0700 | [diff] [blame] | 303 | * after the change |
| 304 | */ |
| 305 | int sandbox_sdl_set_bpp(struct udevice *dev, enum video_log2_bpp l2bpp); |
| 306 | |
Simon Glass | 161e1e3 | 2022-07-30 15:52:22 -0600 | [diff] [blame] | 307 | /** |
| 308 | * sandbox_set_fake_efi_mgr_dev() - Control EFI bootmgr producing valid bootflow |
| 309 | * |
| 310 | * This is only used for testing. |
| 311 | * |
| 312 | * @dev: efi_mgr bootmeth device |
| 313 | * @fake_dev: true to produce a valid bootflow when requested, false to produce |
| 314 | * an error |
| 315 | */ |
| 316 | void sandbox_set_fake_efi_mgr_dev(struct udevice *dev, bool fake_dev); |
| 317 | |
Simon Glass | 45be32c | 2014-12-10 08:55:51 -0700 | [diff] [blame] | 318 | #endif |