Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2019 Toradex |
| 4 | */ |
| 5 | |
| 6 | #ifndef __COLIBRI_IMX8X_H |
| 7 | #define __COLIBRI_IMX8X_H |
| 8 | |
| 9 | #include <asm/arch/imx-regs.h> |
| 10 | #include <linux/sizes.h> |
| 11 | |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 12 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 13 | "fdt_addr_r=0x83000000\0" \ |
| 14 | "kernel_addr_r=0x81000000\0" \ |
| 15 | "ramdisk_addr_r=0x83800000\0" \ |
| 16 | "scriptaddr=0x80800000\0" |
| 17 | |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 18 | /* Boot M4 */ |
| 19 | #define M4_BOOT_ENV \ |
| 20 | "m4_0_image=m4_0.bin\0" \ |
Andrejs Cainikovs | b99fc89 | 2023-03-03 14:26:36 +0100 | [diff] [blame^] | 21 | "loadm4image_0=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ |
| 22 | "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 23 | |
Marcel Ziswiler | acf2a26 | 2023-03-03 14:26:29 +0100 | [diff] [blame] | 24 | /* Enable Distro Boot */ |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 25 | #define BOOT_TARGET_DEVICES(func) \ |
| 26 | func(MMC, mmc, 1) \ |
| 27 | func(MMC, mmc, 0) \ |
| 28 | func(DHCP, dhcp, na) |
| 29 | #include <config_distro_bootcmd.h> |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 30 | |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 31 | /* Initial environment variables */ |
Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 32 | #define CFG_EXTRA_ENV_SETTINGS \ |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 33 | BOOTENV \ |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 34 | M4_BOOT_ENV \ |
| 35 | MEM_LAYOUT_ENV_SETTINGS \ |
Igor Opaniuk | 84c1a2d | 2022-04-13 11:33:27 +0200 | [diff] [blame] | 36 | "boot_script_dhcp=boot.scr\0" \ |
Philippe Schenker | 31a2be5 | 2023-03-03 14:26:27 +0100 | [diff] [blame] | 37 | "console=ttyLP3\0" \ |
Andrejs Cainikovs | a4d8154 | 2023-03-03 14:26:33 +0100 | [diff] [blame] | 38 | "fdt_board=eval-v3\0" \ |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 39 | "initrd_addr=0x83800000\0" \ |
| 40 | "initrd_high=0xffffffffffffffff\0" \ |
Philippe Schenker | 31a2be5 | 2023-03-03 14:26:27 +0100 | [diff] [blame] | 41 | "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \ |
| 42 | "consoleblank=0 earlycon\0" \ |
Marcel Ziswiler | 22a75ed | 2023-03-03 14:26:31 +0100 | [diff] [blame] | 43 | "update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \ |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 44 | "if test \"$confirm\" = \"y\"; then " \ |
| 45 | "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ |
| 46 | "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ |
Andrejs Cainikovs | 943d4f6 | 2023-03-03 14:26:34 +0100 | [diff] [blame] | 47 | "${blkcnt}; fi\0" |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 48 | |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 49 | #define CFG_SYS_SDRAM_BASE 0x80000000 |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 50 | #define PHYS_SDRAM_1 0x80000000 |
| 51 | #define PHYS_SDRAM_2 0x880000000 |
| 52 | #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ |
| 53 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ |
| 54 | |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 55 | /* Generic Timer Definitions */ |
Marcel Ziswiler | 99d768b | 2019-05-31 18:56:39 +0300 | [diff] [blame] | 56 | |
| 57 | #define BOOTAUX_RESERVED_MEM_BASE 0x88000000 |
| 58 | #define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ |
| 59 | |
| 60 | #endif /* __COLIBRI_IMX8X_H */ |