Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b17003f50a707722d1f485fd25570a32bea3d4a7 / . / arch / arm / dts / imx6ull-dart-6ul.dtsi
blob: fed40b01093a03b060a36d4718e252d3bed2434c [file] [log] [blame]
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
4 */
5
6/ {
7 model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
8 compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
9
10 memory {
11 reg = <0x80000000 0x20000000>;
12 };
13
14 chosen {
15 stdout-path = &uart1;
16 };
Marc Ferlandb17003f2020-12-22 14:24:11 -0500[diff] [blame^]17
18 aliases {
19 eeprom0 = &eeprom_som;
20 };
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +0200[diff] [blame]21};
22
23&fec1 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_enet1>;
26 phy-mode = "rmii";
27 phy-handle = <&ethphy0>;
28 status = "okay";
29
30 mdio1: mdio1 {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 ethphy0: ethernet-phy@1 {
35 reg = <1>;
36 micrel,led-mode = <1>;
37 };
38 };
39};
40
41&fec2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_enet2>;
44 phy-mode = "rmii";
45 phy-handle = <&ethphy1>;
46 status = "okay";
47
48 mdio2: mdio2 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ethphy1: ethernet-phy@2 {
53 reg = <2>;
54 micrel,led-mode = <1>;
55 };
56 };
57};
58
59&gpmi {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_gpmi_nand>;
62 nand-on-flash-bbt;
63 fsl,no-blockmark-swap;
64 status = "disabled";
65
66 #address-cells = <1>;
67 #size-cells = <1>;
68
69 partition@0 {
70 label = "uboot";
71 reg = <0x0 0x400000>;
72 };
73
74 partition@400000 {
75 label = "uboot-env";
76 reg = <0x400000 0x100000>;
77 };
78
79 partition@500000 {
80 label = "root";
81 reg = <0x500000 0x0>;
82 };
83};
84
85&i2c1 {
86 clock-frequency = <100000>;
87 pinctrl-names = "default", "gpio";
88 pinctrl-0 = <&pinctrl_i2c1>;
89 pinctrl-1 = <&pinctrl_i2c1_gpio>;
90 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
91 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
92 status = "okay";
93};
94
95&i2c2 {
96 clock-frequency = <100000>;
97 pinctrl-names = "default", "gpio";
98 pinctrl-0 = <&pinctrl_i2c2>;
99 pinctrl-1 = <&pinctrl_i2c2_gpio>;
100 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
101 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
102 status = "okay";
103
Marc Ferlandb17003f2020-12-22 14:24:11 -0500[diff] [blame^]104 eeprom_som: eeprom@50 {
105 compatible = "atmel,24c04";
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +0200[diff] [blame]106 reg = <0x50>;
Marc Ferlandb17003f2020-12-22 14:24:11 -0500[diff] [blame^]107 status = "okay";
Parthiban Nallathambi5e9147d2019-04-18 00:04:09 +0200[diff] [blame]108 };
109};
110
111&pwm1 {
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_pwm1>;
114 #pwm-cells = <3>;
115 status = "okay";
116};
117
118&uart1 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_uart1>;
121 status = "okay";
122};
123
124&usdhc1 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_usdhc1>;
127 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
128 bus-width = <0x4>;
129 no-1-8-v;
130 status = "okay";
131};
132
133&usdhc2 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_usdhc2>;
136 bus-width = <8>;
137 no-1-8-v;
138 non-removable;
139 keep-power-in-suspend;
140 status = "disabled";
141};
142
143&iomuxc {
144 pinctrl-names = "default";
145
146 pinctrl_enet1: enet1grp {
147 fsl,pins = <
148 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
149 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
150 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
151 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
152 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
153 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
154 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
155 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
156 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
157 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
158 >;
159 };
160
161 pinctrl_enet2: enet2grp {
162 fsl,pins = <
163 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
164 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0X1b0b0
165 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
166 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
167 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
168 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
169 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
170 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
171 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
172 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
173 >;
174 };
175
176 pinctrl_gpmi_nand: gpminandgrp {
177 fsl,pins = <
178 MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
179 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
180 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
181 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
182 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
183 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
184 MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
185 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
186 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
187 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
188 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
189 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
190 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
191 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
192 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
193 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
194 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
195 >;
196 };
197
198 pinctrl_i2c1: i2cgrp {
199 fsl,pins = <
200 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
201 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
202 >;
203 };
204
205 pinctrl_i2c1_gpio: i2c1grp_gpio {
206 fsl,pins = <
207 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
208 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
209 >;
210 };
211
212 pinctrl_i2c2: i2cgrp {
213 fsl,pins = <
214 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
215 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
216 >;
217 };
218
219 pinctrl_i2c2_gpio: i2c2grp_gpio {
220 fsl,pins = <
221 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
222 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
223 >;
224 };
225
226 pinctrl_pwm1: pwm1grp {
227 fsl,pins = <
228 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1
229 >;
230 };
231
232 pinctrl_uart1: uart1grp {
233 fsl,pins = <
234 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
235 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
236 >;
237 };
238
239 pinctrl_usdhc1: usdhc1grp {
240 fsl,pins = <
241 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
242 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
243 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
244 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
245 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
246 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
247 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
248
249 >;
250 };
251
252 pinctrl_usdhc2: usdhc2grp {
253 fsl,pins = <
254 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
255 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
256 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
257 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
258 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
259 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
260 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
261 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
262 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
263 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
264 >;
265 };
266};