blob: 06a3a832984ef22dc59bdcf0211d51c985df2226 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasut3ef6d082017-10-08 20:41:18 +02002/*
3 * board/renesas/draak/draak.c
4 * This file is Draak board support.
5 *
6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut3ef6d082017-10-08 20:41:18 +02007 */
8
Simon Glassafb02152019-12-28 10:45:01 -07009#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -070010#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Marek Vasut3ef6d082017-10-08 20:41:18 +020012#include <malloc.h>
13#include <netdev.h>
14#include <dm.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Marek Vasut3ef6d082017-10-08 20:41:18 +020016#include <dm/platform_data/serial_sh.h>
17#include <asm/processor.h>
18#include <asm/mach-types.h>
19#include <asm/io.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060020#include <linux/bitops.h>
Marek Vasut3ef6d082017-10-08 20:41:18 +020021#include <linux/errno.h>
22#include <asm/arch/sys_proto.h>
23#include <asm/gpio.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/rmobile.h>
26#include <asm/arch/rcar-mstp.h>
27#include <asm/arch/sh_sdhi.h>
28#include <i2c.h>
29#include <mmc.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
Marek Vasut3ef6d082017-10-08 20:41:18 +020033#define GSX_MSTP112 BIT(12) /* 3DG */
Marek Vasut3ef6d082017-10-08 20:41:18 +020034#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
35#define DVFS_MSTP926 BIT(26)
36#define HSUSB_MSTP704 BIT(4) /* HSUSB */
37
38int board_early_init_f(void)
39{
Tom Rini52b2e262021-08-18 23:12:24 -040040#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
Marek Vasut3ef6d082017-10-08 20:41:18 +020041 /* DVFS for reset */
Hiroyuki Yokoyama7e172912018-09-26 16:00:09 +090042 mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
Marek Vasut3ef6d082017-10-08 20:41:18 +020043#endif
44 return 0;
45}
46
Marek Vasut3ef6d082017-10-08 20:41:18 +020047/* HSUSB block registers */
48#define HSUSB_REG_LPSTS 0xE6590102
49#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
50#define HSUSB_REG_UGCTRL2 0xE6590184
51#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
52#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
53
54int board_init(void)
55{
Marek Vasut3ef6d082017-10-08 20:41:18 +020056 /* USB1 pull-up */
57 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
58
59 /* Configure the HSUSB block */
Hiroyuki Yokoyama7e172912018-09-26 16:00:09 +090060 mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
Marek Vasut3ef6d082017-10-08 20:41:18 +020061 /* Choice USB0SEL */
62 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
63 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
64 /* low power status */
65 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
66
67 return 0;
68}