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git01.mediatek.com / filogic / uboot / 20c49dac78b9952f2dc7e62ff0438a04a2b8b153 / . / drivers / video / omap3_dss.c
blob: b322cc35796c24294105d66da559d2ab119d2cad [file] [log] [blame]
Syed Mohammed Khasim49ef8d42011-04-19 14:00:34 -0500[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 * Syed Mohammed Khasim <khasim@ti.com>
5 *
6 * Referred to Linux Kernel DSS driver files for OMAP3 by
7 * Tomi Valkeinen from drivers/video/omap2/dss/
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation's version 2 and any
15 * later version the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <asm/io.h>
30#include <asm/arch/dss.h>
31
32/*
33 * Configure VENC for a given Mode (NTSC / PAL)
34 */
35void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
36 u32 height, u32 width)
37{
38 struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
39 struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
40 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
41
42 writel(venc_cfg->status, &venc->status);
43 writel(venc_cfg->f_control, &venc->f_control);
44 writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
45 writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
46 writel(venc_cfg->llen, &venc->llen);
47 writel(venc_cfg->flens, &venc->flens);
48 writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
49 writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
50 writel(venc_cfg->c_phase, &venc->c_phase);
51 writel(venc_cfg->gain_u, &venc->gain_u);
52 writel(venc_cfg->gain_v, &venc->gain_v);
53 writel(venc_cfg->gain_y, &venc->gain_y);
54 writel(venc_cfg->black_level, &venc->black_level);
55 writel(venc_cfg->blank_level, &venc->blank_level);
56 writel(venc_cfg->x_color, &venc->x_color);
57 writel(venc_cfg->m_control, &venc->m_control);
58 writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
59 writel(venc_cfg->s_carr, &venc->s_carr);
60 writel(venc_cfg->line21, &venc->line21);
61 writel(venc_cfg->ln_sel, &venc->ln_sel);
62 writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
63 writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
64 writel(venc_cfg->savid__eavid, &venc->savid__eavid);
65 writel(venc_cfg->flen__fal, &venc->flen__fal);
66 writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
67 writel(venc_cfg->hs_int_start_stop_x,
68 &venc->hs_int_start_stop_x);
69 writel(venc_cfg->hs_ext_start_stop_x,
70 &venc->hs_ext_start_stop_x);
71 writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
72 writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
73 &venc->vs_int_stop_x__vs_int_start_y);
74 writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
75 &venc->vs_int_stop_y__vs_ext_start_x);
76 writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
77 &venc->vs_ext_stop_x__vs_ext_start_y);
78 writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
79 writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
80 writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
81 writel(venc_cfg->fid_int_start_x__fid_int_start_y,
82 &venc->fid_int_start_x__fid_int_start_y);
83 writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
84 &venc->fid_int_offset_y__fid_ext_start_x);
85 writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
86 &venc->fid_ext_start_y__fid_ext_offset_y);
87 writel(venc_cfg->tvdetgp_int_start_stop_x,
88 &venc->tvdetgp_int_start_stop_x);
89 writel(venc_cfg->tvdetgp_int_start_stop_y,
90 &venc->tvdetgp_int_start_stop_y);
91 writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
92 writel(venc_cfg->output_control, &venc->output_control);
93 writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
94
95 /* Configure DSS for VENC Settings */
96 writel(VENC_DSS_CONFIG, &dss->control);
97
98 /* Configure height and width for Digital out */
99 writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
100}
101
102/*
103 * Configure Panel Specific Parameters
104 */
105void omap3_dss_panel_config(const struct panel_config *panel_cfg)
106{
107 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
108
109 writel(panel_cfg->timing_h, &dispc->timing_h);
110 writel(panel_cfg->timing_v, &dispc->timing_v);
111 writel(panel_cfg->pol_freq, &dispc->pol_freq);
112 writel(panel_cfg->divisor, &dispc->divisor);
113 writel(panel_cfg->lcd_size, &dispc->size_lcd);
114 writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
115 writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
116 (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
117 writel(panel_cfg->panel_color, &dispc->default_color0);
118}
119
120/*
121 * Enable LCD and DIGITAL OUT in DSS
122 */
123void omap3_dss_enable(void)
124{
125 struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
126 u32 l = 0;
127
128 l = readl(&dispc->control);
129 l |= DISPC_ENABLE;
130 writel(l, &dispc->control);
131}