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git01.mediatek.com / filogic / uboot / 53fbdd1a5ca8206ef582e4b80fb0f7cf854c0c9f / . / arch / powerpc / dts / gazerbeam.dts
blob: a4408c496c8ea6e45d0a87e8c53993a5204e7cdd [file] [log] [blame]
Mario Six53fbdd12019-03-29 10:18:17 +0100[diff] [blame^]1/*
2 * Gazerbeam CON Device Tree Source
3 *
4 * (C) Copyright 2015
5 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13/include/ "gdsys/mpc8308.dtsi"
14
15/include/ "gdsys/gazerbeam-base.dtsi"
16
17/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
18/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
19/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
20/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
21
22&board_lbc {
23 FPGA0:iocon_uart@1,0 {
24 reg = <0x1 0x0 0x100000>;
25 little-endian;
26 interrupts = <48 0x8>;
27 interrupt-parent = <&ipic>;
28 };
29
30 FPGA1:iocon_uart@2,0 {
31 reg = <0x2 0x0 0x100000>;
32 little-endian;
33 interrupts = <17 0x8>;
34 interrupt-parent = <&ipic>;
35 };
36};
37
38&FPGA0 {
39 compatible = "gdsys,iocon_fpga";
40 #gpio-cells = <2>;
41 gpio-controller;
42 bus = <&FPGA0BUS>;
43 unit_id = <0>;
44 fpga-type = <1>;
45 usb_base = <0x0080>;
46 audio_base = <0x0040>;
47 timebase_base = <0x013c>;
48
49 /*
50 * for every interrupt source there must be a dataset specifying
51 * 1. type (1: standard)
52 * 2. status register offset
53 * 3. mask register offset
54 * 4. default mask
55 */
56 fpga_interrupt_sources =
57 <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
58 <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
59 /*
60 * for every interrupt there must be a dataset specifying
61 * 1. type (1: status, 2: event)
62 * 2. interrupt source index
63 * 3. interrupt register bit
64 * 4. mask register bit
65 */
66 #fpga_interrupt_map-cells = <4>;
67 fpga_interrupt_map =
68 <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
69 <1 0 0 0>, /* 1: VIDEO 0 */
70 <1 0 1 1>, /* 2: VIDEO 1 */
71 <1 0 2 2>, /* 3: VIDEO IC 0 */
72 <1 0 3 3>, /* 4: VIDEO IC 1 */
73 <1 0 4 4>, /* 5: IIC MAIN */
74 <1 0 6 6>, /* 6: IIC VIDEO 0 */
75 <1 0 7 7>, /* 7: IIC VIDEO 1 */
76 <1 1 0 0>, /* 8: OSD 0 */
77 <1 1 1 1>, /* 9: OSD 1 */
78 <1 1 2 2>, /* 10: SPDIF 0 */
79 <1 1 3 3>, /* 11: SPDIF 1 */
80 <1 0 12 12>, /* 12: COMM 0 */
81 <1 0 13 13>, /* 13: COMM 1 */
82 <1 0 10 10>, /* 14: COMM 2 */
83 <1 0 11 11>, /* 15: COMM 3 */
84 <2 0 5 5>, /* 16: MDIO */
85 <1 0 8 8>, /* 17: PHY */
86 <1 1 4 4>, /* 18: RS232 */
87 <1 1 5 5>, /* 19: AUDIO */
88 <1 1 8 8>, /* 20: PROC_AUDIO */
89 <1 1 7 7>, /* 21: USB/ETH-UART INT */
90 <2 1 10 10>, /* 22: AXI Bridge 0 */
91 <2 1 11 11>, /* 23: AXI Bridge 1 */
92 <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
93 <>;
94};
95
96&FPGA1 {
97 compatible = "gdsys,iocon_fpga";
98 #gpio-cells = <2>;
99 gpio-controller;
100 bus = <&FPGA1BUS>;
101 unit_id = <1>;
102 fpga-type = <1>;
103 usb_base = <0x0070>;
104 audio_base = <0x0040>;
105 timebase_base = <0x013c>;
106
107 /*
108 * for every interrupt source there must be a dataset specifying
109 * 1. type (1: standard)
110 * 2. status register offset
111 * 3. mask register offset
112 * 4. default mask
113 */
114 fpga_interrupt_sources =
115 <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
116 <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
117 /*
118 * for every interrupt there must be a dataset specifying
119 * 1. type (1: status, 2: event)
120 * 2. interrupt source index
121 * 3. interrupt register bit
122 * 4. mask register bit
123 */
124 #fpga_interrupt_map-cells = <4>;
125 fpga_interrupt_map =
126 <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
127 <1 0 0 0>, /* 1: VIDEO 0 */
128 <1 0 1 1>, /* 2: VIDEO 1 */
129 <1 0 2 2>, /* 3: VIDEO IC 0 */
130 <1 0 3 3>, /* 4: VIDEO IC 1 */
131 <1 0 4 4>, /* 5: IIC MAIN */
132 <1 0 6 6>, /* 6: IIC VIDEO 0 */
133 <1 0 7 7>, /* 7: IIC VIDEO 1 */
134 <1 1 0 0>, /* 8: OSD 0 */
135 <1 1 1 1>, /* 9: OSD 1 */
136 <1 1 2 2>, /* 10: SPDIF 0 */
137 <1 1 3 3>, /* 11: SPDIF 1 */
138 <1 0 12 12>, /* 12: COMM 0 */
139 <1 0 13 13>, /* 13: COMM 1 */
140 <1 0 10 10>, /* 14: COMM 2 */
141 <1 0 11 11>, /* 15: COMM 3 */
142 <2 0 5 5>, /* 16: MDIO */
143 <1 0 8 8>, /* 17: PHY */
144 <1 1 4 4>, /* 18: RS232 */
145 <1 1 5 5>, /* 19: AUDIO */
146 <1 1 8 8>, /* 20: PROC_AUDIO */
147 <1 1 7 7>, /* 21: USB/ETH-UART INT */
148 <2 1 10 10>, /* 22: AXI Bridge 0 */
149 <2 1 11 11>, /* 23: AXI Bridge 1 */
150 <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
151 <>;
152};
153
154/ {
155 FPGA0BUS: fpga0bus {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0 0 0x00002000>;
159
160 compatible = "gdsys,soc";
161
162 fpga0_rs232 {
163 compatible = "gdsys,ihs_trans_rs232";
164 reg = <0x50 0x08>;
165 little-endian;
166 };
167
168 fpga0_uart_usb {
169 compatible = "gdsys,ihs_simple_uart";
170 reg = <0xa0 0x08>;
171 little-endian;
172 fpga_interrupts = <21>;
173 line = <0>;
174 };
175
176 fpga0_iic_main {
177 compatible = "gdsys,ihs_i2cmaster";
178 reg = <0x60 0x10>;
179 little-endian;
180 fpga_interrupts = <5>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
185 compatible = "ti,sn75dp130";
186 reg = <0x2c>;
187 eq-i2c-enable = <3 2 1 0
188 3 2 1 0
189 3 2 1 0
190 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
191 };
192 fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
193 compatible = "ti,sn75dp130";
194 reg = <0x2e>;
195 eq-i2c-enable = <3 2 1 0
196 3 2 1 0
197 3 2 1 0
198 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
199 };
200 lm77@48 {
201 compatible = "national,lm77";
202 reg = <0x48>;
203 };
204 ads1015@49 {
205 compatible = "ti,ads1015";
206 reg = <0x49>;
207 };
208 ads1015@4b {
209 compatible = "ti,ads1015";
210 reg = <0x4b>;
211 };
212 };
213
214 fpga0_video0 {
215 compatible = "gdsys,ihs_video_out";
216 reg = <0x100 0x40>;
217 little-endian;
218 fpga_interrupts = <1 8>; /* VIDEO OSD */
219 osd_base = <0x180>;
220 osd_buffer_base = <0x1000>;
221 spdif_audio_base = <0x1e0>;
222 video_index = <0>;
223 video_id = <0>;
224 fpga-force-pos-pol;
225 sync-source;
226 fpga-pb-pixels = <2730>; /* 8192 / 3 */
227 fpga-ra-lines = <2>;
228 video_tx = <&fpga0_dp_video0>;
229 clk_gen = <&fpga0_video0_clkgen>;
230 ddc_ci = <&fpga0_dp_video0>;
231 };
232
233 fpga0_iic_video0 {
234 compatible = "gdsys,ihs_i2cmaster";
235 reg = <0x1c0 0x10>;
236 little-endian;
237 fpga_interrupts = <6>;
238 #address-cells = <1>;
239 #size-cells = <0>;
240
241 fpga0_video0_clkgen: fpga0_video0_clkgen {
242 compatible = "idt,ics8n3qv01";
243 reg = <0x6e>;
244 channel = <0>;
245 };
246 };
247
248 fpga0_axi_video0 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 compatible = "gdsys,ihs_axi";
252 reg = <0x170 0x10>;
253 little-endian;
254 fpga_interrupts = <22>;
255
256 fpga0_dp_video0: fpga0_dp_video0 {
257 compatible = "gdsys,logicore_dp_tx";
258 reg = <0x44a10000 0x1000>;
259 little-endian;
260 redriver = <&fpga0_dp_video0_redriver>;
261 video_id = <0>;
262 };
263 };
264
265 fpga0_video1 {
266 compatible = "gdsys,ihs_video_out";
267 reg = <0x200 0x40>;
268 little-endian;
269 fpga_interrupts = <2 9>; /* VIDEO OSD */
270 osd_base = <0x280>;
271 osd_buffer_base = <0x2000>;
272 spdif_audio_base = <0x2e0>;
273 video_index = <1>;
274 video_id = <1>;
275 fpga-force-pos-pol;
276 sync-source;
277 fpga-pb-pixels = <2730>; /* 8192 / 3 */
278 fpga-ra-lines = <2>;
279 video_tx = <&fpga0_dp_video1>;
280 clk_gen = <&fpga0_video1_clkgen>;
281 ddc_ci = <&fpga0_dp_video1>;
282 };
283
284 fpga0_iic_video1 {
285 compatible = "gdsys,ihs_i2cmaster";
286 reg = <0x2c0 0x10>;
287 little-endian;
288 fpga_interrupts = <7>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 fpga0_video1_clkgen: fpga0_video1_clkgen {
293 compatible = "idt,ics8n3qv01";
294 reg = <0x6e>;
295 channel = <1>;
296 };
297 };
298
299 fpga0_axi_video1 {
300 #address-cells = <1>;
301 #size-cells = <1>;
302 compatible = "gdsys,ihs_axi";
303 reg = <0x270 0x10>;
304 little-endian;
305 fpga_interrupts = <23>;
306
307 fpga0_dp_video1: fpga0_dp_video1 {
308 compatible = "gdsys,logicore_dp_tx";
309 reg = <0x44a10000 0x1000>;
310 little-endian;
311 redriver = <&fpga0_dp_video1_redriver>;
312 video_id = <1>;
313 };
314 };
315
316 fpga0_iic_usb {
317 compatible = "gdsys,ihs_i2cmaster";
318 reg = <0xb0 0x10>;
319 little-endian;
320 fpga_interrupts = <24>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323
324 pca9555@20 {
325 compatible = "nxp,pca9555";
326 reg = <0x20>;
327 #gpio-cells = <2>;
328 gpio-controller;
329 };
330 };
331
332 fpga0_ep0 {
333 compatible = "gdsys,io-endpoint";
334 reg = < 0x020 0x10
335 0x320 0x10
336 0x340 0x10
337 0x360 0x10>;
338 little-endian;
339 irq-model-local;
340 fpga_interrupts = <12 13 14 15>;
341 pollcycle = <200>;
342 nprot_channel = <16>;
343 uart_line = <0>;
344 ep_index = <0>;
345 line_protocol = <1>;
346 };
347
348 fpga0_mdio {
349 compatible = "gdsys,ihs_mdiomaster";
350 reg = <0x0058 0x10>;
351 little-endian;
352 fpga_interrupts = <16>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355
356 fpga0_phy0 {
357 compatible = "ethernet-phy-ieee802.3-c45";
358 device_type ="ethernet-phy";
359 reg = <0>;
360 };
361 fpga0_phy1 {
362 compatible = "ethernet-phy-ieee802.3-c45";
363 device_type ="ethernet-phy";
364 reg = <1>;
365 };
366 fpga0_phy2 {
367 compatible = "ethernet-phy-ieee802.3-c45";
368 device_type ="ethernet-phy";
369 reg = <2>;
370 };
371 fpga0_phy3 {
372 compatible = "ethernet-phy-ieee802.3-c45";
373 device_type ="ethernet-phy";
374 reg = <3>;
375 };
376 };
377
378 };
379
380
381 FPGA1BUS: fpga1bus {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 ranges = <0 0 0x00002000>;
385
386 compatible = "gdsys,soc";
387
388 fpga1_uart_usb {
389 compatible = "gdsys,ihs_simple_uart";
390 reg = <0xa0 0x08>;
391 little-endian;
392 fpga_interrupts = <21>;
393 line = <4>; /* TODO check and FIX */
394 };
395
396 fpga1_iic_main {
397 compatible = "gdsys,ihs_i2cmaster";
398 reg = <0x60 0x10>;
399 little-endian;
400 fpga_interrupts = <5>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403
404 fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
405 compatible = "ti,sn75dp130";
406 reg = <0x2c>;
407 eq-i2c-enable = <3 2 1 0
408 3 2 1 0
409 3 2 1 0
410 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
411 };
412 fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
413 compatible = "ti,sn75dp130";
414 reg = <0x2e>;
415 eq-i2c-enable = <3 2 1 0
416 3 2 1 0
417 3 2 1 0
418 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
419 };
420 lm77@48 {
421 compatible = "national,lm77";
422 reg = <0x48>;
423 };
424 ads1015@49 {
425 compatible = "ti,ads1015";
426 reg = <0x49>;
427 };
428 ads1015@4b {
429 compatible = "ti,ads1015";
430 reg = <0x4b>;
431 };
432 };
433
434 fpga1_video0 {
435 compatible = "gdsys,ihs_video_out";
436 reg = <0x100 0x40>;
437 little-endian;
438 fpga_interrupts = <1 8>; /* VIDEO OSD */
439 osd_base = <0x180>;
440 osd_buffer_base = <0x1000>;
441 spdif_audio_base = <0x1e0>;
442 video_index = <0>;
443 video_id = <4>;
444 fpga-force-pos-pol;
445 sync-source;
446 fpga-pb-pixels = <2730>; /* 8192 / 3 */
447 fpga-ra-lines = <2>;
448 video_tx = <&fpga1_dp_video0>;
449 clk_gen = <&fpga1_video0_clkgen>;
450 ddc_ci = <&fpga1_dp_video0>;
451 };
452
453 fpga1_iic_video0 {
454 compatible = "gdsys,ihs_i2cmaster";
455 reg = <0x1c0 0x10>;
456 little-endian;
457 fpga_interrupts = <6>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460
461 fpga1_video0_clkgen: fpga1_video0_clkgen {
462 compatible = "idt,ics8n3qv01";
463 reg = <0x6e>;
464 channel = <4>;
465 };
466 };
467
468 fpga1_axi_video0 {
469 #address-cells = <1>;
470 #size-cells = <1>;
471 compatible = "gdsys,ihs_axi";
472 reg = <0x170 0x10>;
473 little-endian;
474 fpga_interrupts = <22>;
475
476 fpga1_dp_video0: fpga1_dp_video0 {
477 compatible = "gdsys,logicore_dp_tx";
478 reg = <0x44a10000 0x1000>;
479 little-endian;
480 redriver = <&fpga1_dp_video0_redriver>;
481 video_id = <4>;
482 };
483 };
484
485 fpga1_video1 {
486 compatible = "gdsys,ihs_video_out";
487 reg = <0x200 0x40>;
488 little-endian;
489 fpga_interrupts = <2 9>; /* VIDEO OSD */
490 osd_base = <0x280>;
491 osd_buffer_base = <0x2000>;
492 spdif_audio_base = <0x2e0>;
493 video_index = <1>;
494 video_id = <5>;
495 fpga-force-pos-pol;
496 sync-source;
497 fpga-pb-pixels = <2730>; /* 8192 / 3 */
498 fpga-ra-lines = <2>;
499 video_tx = <&fpga1_dp_video1>;
500 clk_gen = <&fpga1_video1_clkgen>;
501 ddc_ci = <&fpga1_dp_video1>;
502 };
503
504 fpga1_iic_video1 {
505 compatible = "gdsys,ihs_i2cmaster";
506 reg = <0x2c0 0x10>;
507 little-endian;
508 fpga_interrupts = <7>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511
512 fpga1_video1_clkgen: fpga1_video1_clkgen {
513 compatible = "idt,ics8n3qv01";
514 reg = <0x6e>;
515 channel = <5>;
516 };
517 };
518
519 fpga1_axi_video1 {
520 #address-cells = <1>;
521 #size-cells = <1>;
522 compatible = "gdsys,ihs_axi";
523 reg = <0x270 0x10>;
524 little-endian;
525 fpga_interrupts = <23>;
526
527 fpga1_dp_video1: fpga1_dp_video1 {
528 compatible = "gdsys,logicore_dp_tx";
529 reg = <0x44a10000 0x1000>;
530 little-endian;
531 redriver = <&fpga1_dp_video1_redriver>;
532 video_id = <5>;
533 };
534 };
535
536 fpga1_iic_usb {
537 compatible = "gdsys,ihs_i2cmaster";
538 reg = <0xb0 0x10>;
539 little-endian;
540 fpga_interrupts = <24>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543
544 pca9555@20 {
545 compatible = "nxp,pca9555";
546 reg = <0x20>;
547 #gpio-cells = <2>;
548 gpio-controller;
549 };
550 };
551
552 fpga1_ep0 {
553 compatible = "gdsys,io-endpoint";
554 reg = < 0x020 0x10
555 0x320 0x10
556 0x340 0x10
557 0x360 0x10>;
558 little-endian;
559 irq-model-local;
560 fpga_interrupts = <12 13 14 15>;
561 pollcycle = <200>;
562 nprot_channel = <17>;
563 uart_line = <1>;
564 ep_index = <0>;
565 line_protocol = <1>;
566 };
567
568 fpga1_mdio {
569 compatible = "gdsys,ihs_mdiomaster";
570 reg = <0x0058 0x10>;
571 little-endian;
572 fpga_interrupts = <16>;
573 #address-cells = <1>;
574 #size-cells = <0>;
575
576 fpga1_phy0 {
577 compatible = "ethernet-phy-ieee802.3-c45";
578 device_type ="ethernet-phy";
579 reg = <0>;
580 };
581 fpga1_phy1 {
582 compatible = "ethernet-phy-ieee802.3-c45";
583 device_type ="ethernet-phy";
584 reg = <1>;
585 };
586 fpga1_phy2 {
587 compatible = "ethernet-phy-ieee802.3-c45";
588 device_type ="ethernet-phy";
589 reg = <2>;
590 };
591 fpga1_phy3 {
592 compatible = "ethernet-phy-ieee802.3-c45";
593 device_type ="ethernet-phy";
594 reg = <3>;
595 };
596 };
597
598 };
599
600};