Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 53e005910595c5a2974c0361caaa4183f21ce3a3 / . / board / teejet / mt_ventoux / mt_ventoux.h
blob: 1cd7ec2ab290950f2b7a1137c901d41af490279c [file] [log] [blame]
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Stefano Babic <sbabic@denx.de>
3 *
4 * Author: Hardy Weng <hardy.weng@technexion.com>
5 *
6 * Copyright (C) 2010 TechNexion Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc.
21 */
22
23#ifndef _MT_VENTOUX_H_
24#define _MT_VENTOUX_H_
25
26const omap3_sysinfo sysinfo = {
27 DDR_DISCRETE,
28 "Teejet MT_VENTOUX Board",
29 "NAND",
30};
31
32/* FPGA CS1 configuration */
33#define FPGA_GPMC_CONFIG1 0x00001200
Stefano Babic830d70f2012-03-21 00:14:24 +0000[diff] [blame]34#define FPGA_GPMC_CONFIG2 0x00161f00
35#define FPGA_GPMC_CONFIG3 0x00040400
36#define FPGA_GPMC_CONFIG4 0x120c1f08
37#define FPGA_GPMC_CONFIG5 0x001e161f
38#define FPGA_GPMC_CONFIG6 0x96080fcf
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]39
40#define FPGA_BASE_ADDR 0x20000000
41
42/*
43 * IEN - Input Enable
44 * IDIS - Input Disable
45 * PTD - Pull type Down
46 * PTU - Pull type Up
47 * DIS - Pull type selection is inactive
48 * EN - Pull type selection is active
49 * M0 - Mode 0
50 * The commented string gives the final mux configuration for that pin
51 */
52#define MUX_MT_VENTOUX() \
53 /* SDRC */\
54 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
55 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
56 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
57 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
58 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
59 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
60 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
61 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
62 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
63 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
64 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
65 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
66 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
67 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
68 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
69 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
70 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
71 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
72 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
73 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
74 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
75 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
76 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
77 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
78 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
79 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
80 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
81 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
82 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
83 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
84 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
85 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
86 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
87 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
88 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
89 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
90 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
91 MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
92 MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
93 MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
94 MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
95 MUX_VAL(CP(SDRC_CKE0), (M0)) \
96 MUX_VAL(CP(SDRC_CKE1), (M0)) \
97 MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
98 MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
99 /* GPMC */\
100 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
101 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
102 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
103 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
104 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
105 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
106 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
107 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
108 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
109 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
110 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
111 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
112 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
113 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
114 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
115 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
116 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
117 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
118 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
119 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
120 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
121 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
122 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
123 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
124 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
125 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
126 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
127 MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
128 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
129 MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
130 MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
131 /* GPIO 55 : NFS */\
132 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
133 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
134 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
135 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
136 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
137 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
138 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
139 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
140 MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
141 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
142 /*GPIO_62: FPGA_RESET */ \
143 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
144 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]145 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
146 /* GPIO_64*/ \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]147 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
148 /* DSS */\
149 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
150 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
151 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
152 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
153 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
154 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
155 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
156 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
157 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
158 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
159 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
160 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
161 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
162 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
163 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
164 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
165 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
166 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
167 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
168 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
169 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
170 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
171 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
172 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
173 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
174 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
175 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
176 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
177 /* CAMERA */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]178 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
179 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
180 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
181 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
182 /* MMC */\
183 MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
184 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
185 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
186 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
187 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
188 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
189 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
190 /* GPIO_126: CardDetect */\
191 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
192 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]193 /*GPIO_128 */ \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]194 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
195 \
196 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
197 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
198 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
199 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
200 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
201 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
202 MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
203 MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
204 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
205 /* GPIO_138: LCD_ENVD */\
Stefano Babicb6320932012-08-29 01:22:07 +0000[diff] [blame]206 MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]207 /* GPIO_139: LCD_PON */\
208 /* McBSP */\
209 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
210 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
211 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
212 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
213 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
214 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
215 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
216 \
217 MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \
218 /* GPIO_116: FPGA_PROG */ \
219 MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
220 /* GPIO_117: FPGA_CCLK */ \
221 MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
222 /* GPIO_118: FPGA_DIN */ \
223 MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
224 /* GPIO_119: FPGA_INIT */ \
225 \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]226 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
227 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
228 \
229 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \
230 /*GPIO_152: Ignition Sense */ \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]231 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]232 /*GPIO_153: Power Button Sense */ \
233 MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \
234 /* GPIO_154: FPGA_DONE */ \
235 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \
236 /* GPIO_155: CA8_irq */ \
237 /* UART */\
238 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
239 MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
240 /* GPIO_149: USB status 2 */\
241 MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
242 /* GPIO_150: USB status 1 */\
243 \
244 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]245 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
246 /* gpt9_pwm */\
247 MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
248 /* gpt10_pwm */\
249 MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
250 /* gpt8_pwm */\
251 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
252 /* gpt11_pwm */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]253 \
254 MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \
255 /*GPIO_163 : TS_PENIRQ*/ \
256 MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \
257 /*GPIO_164 : MMC */\
258 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
259 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
260 /* I2C */\
261 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
262 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
263 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
264 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
265 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
266 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
267 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
268 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
269 /* McSPI */\
270 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
271 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
272 MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
273 MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
274 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
275 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
276 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
277 \
278 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
279 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
280 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
281 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
282 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \
283 /* CCDC */\
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]284 MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \
285 /* GPIO94 */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]286 MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \
287 /* GPIO95: #Enable Output */\
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]288 MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \
289 MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]290 MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \
291 /* GPIO 99: #SOM_PWR_OFF */\
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]292 MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]293 MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \
294 /* GPIO_100: #power out */\
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]295 MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \
296 MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \
297 /* GPIO_102 */\
298 MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \
299 MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \
300 MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \
301 MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]302 /* RMII */\
303 MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
304 MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
305 MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
306 MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
307 MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
308 MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
309 MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
310 MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
311 MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
312 MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
313 /* HECC */\
314 MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
315 MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
316 /* HSUSB */\
317 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
318 MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
319 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
320 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
321 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
322 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
323 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
324 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
325 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
326 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
327 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
328 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
329 MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
330 /* HDQ */\
331 MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
332 /* GPIO_170: auto update */\
333 /* Control and debug */\
334 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
335 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
336 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
337 MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
338 /* - GPIO30 */\
339 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
340 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
341 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
342 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
343 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
344 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
345 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
346 MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
347 MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
348 \
349 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]350 MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \
351 /* gpio_10 */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]352 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
353 /* JTAG */\
354 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
355 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
356 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
357 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
358 MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
359 MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
360 /* ETK (ES2 onwards) */\
361 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
362 /* hsusb1_stp */ \
363 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
364 /* hsusb1_clk */\
365 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
366 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
367 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
368 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
369 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
370 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
371 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
372 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
373 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
374 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]375 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \
376 /* gpio_24 */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]377 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]378 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
379 /* gpio_26 */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]380 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \
Stefano Babic098f4652012-08-29 01:22:01 +0000[diff] [blame]381 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
382 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
383 /* gpio_29 */\
Stefano Babic18db74a2012-02-07 23:29:34 +0000[diff] [blame]384 /* Die to Die */\
385 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
386 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
387 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
388 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
389 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
390 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
391 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
392 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
393 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
394 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
395 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
396 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
397 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
398 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
399 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
400 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
401 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
402 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
403 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
404 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
405 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
406 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
407 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
408 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
409 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
410 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
411 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
412 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
413 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
414 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
415
416#endif