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Stefan Roese115802d2018-08-16 15:27:31 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
7#define __CONFIG_GARDENA_SMART_GATEWAY_H
8
Stefan Roese115802d2018-08-16 15:27:31 +02009/* RAM */
Tom Rinibb4dd962022-11-16 13:10:37 -050010#define CFG_SYS_SDRAM_BASE 0x80000000
Stefan Roese115802d2018-08-16 15:27:31 +020011
Tom Rini6a5dccc2022-11-16 13:10:41 -050012#define CFG_SYS_INIT_SP_OFFSET 0x400000
Stefan Roese115802d2018-08-16 15:27:31 +020013
developer9720bc32020-04-21 09:28:48 +020014/* Dummy value */
Tom Rini6a5dccc2022-11-16 13:10:41 -050015#define CFG_SYS_UBOOT_BASE 0
developer9720bc32020-04-21 09:28:48 +020016
17/* Serial SPL */
Simon Glass209ae762024-09-29 19:49:49 -060018#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rinidf6a2152022-11-16 13:10:28 -050019#define CFG_SYS_NS16550_CLK 40000000
20#define CFG_SYS_NS16550_COM1 0xb0000c00
developer9720bc32020-04-21 09:28:48 +020021#endif
22
Stefan Roese115802d2018-08-16 15:27:31 +020023/* UART */
Tom Rini6a5dccc2022-11-16 13:10:41 -050024#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
developere1693432019-09-25 17:45:42 +080025 230400, 460800, 921600 }
Stefan Roese115802d2018-08-16 15:27:31 +020026
27/* RAM */
Stefan Roese115802d2018-08-16 15:27:31 +020028
Stefan Roese115802d2018-08-16 15:27:31 +020029/* Environment settings */
Stefan Roese115802d2018-08-16 15:27:31 +020030
Stefan Roese115802d2018-08-16 15:27:31 +020031#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */