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git01.mediatek.com / filogic / uboot / 53a55a117fe0526b84b7f2d121230ae4d8ebcf3a / . / drivers / clk / sunxi / clk_h6.c
blob: a1cb8952d39c02768b5511372b214e22fe2a9f3a [file] [log] [blame]
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun50i-h6-ccu.h>
13#include <dt-bindings/reset/sun50i-h6-ccu.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]15
16static struct ccu_clk_gate h6_gates[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
18 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
19 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]20 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
21 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
22 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
23 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]24
25 [CLK_SPI0] = GATE(0x940, BIT(31)),
26 [CLK_SPI1] = GATE(0x944, BIT(31)),
27
28 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
29 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]30
31 [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
Andre Przywara60e6efd2019-06-23 15:09:48 +0100[diff] [blame]32
33 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
34 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
35
36 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
37
38 [CLK_USB_HSIC] = GATE(0xa7c, BIT(26)),
39 [CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)),
40 [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
41 [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
42
43 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
44 [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
45 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
46 [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
47 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]48};
49
50static struct ccu_reset h6_resets[] = {
Andre Przywaraddf33c12019-01-29 15:54:09 +0000[diff] [blame]51 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
52 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
53 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]54 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
55 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
56 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
57 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
Jagan Tekibc123132019-02-27 20:02:06 +0530[diff] [blame]58
59 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
60 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
Jagan Teki836631b2019-02-28 00:26:57 +0530[diff] [blame]61
62 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
Andre Przywara60e6efd2019-06-23 15:09:48 +0100[diff] [blame]63
64 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
65
66 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
67
68 [RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
69 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
70
71 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
72 [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
73 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
74 [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
75 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
Jagan Teki5bc16d22018-12-31 15:35:01 +0530[diff] [blame]76};
77
78static const struct ccu_desc h6_ccu_desc = {
79 .gates = h6_gates,
80 .resets = h6_resets,
81};
82
83static int h6_clk_bind(struct udevice *dev)
84{
85 return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
86}
87
88static const struct udevice_id h6_ccu_ids[] = {
89 { .compatible = "allwinner,sun50i-h6-ccu",
90 .data = (ulong)&h6_ccu_desc },
91 { }
92};
93
94U_BOOT_DRIVER(clk_sun50i_h6) = {
95 .name = "sun50i_h6_ccu",
96 .id = UCLASS_CLK,
97 .of_match = h6_ccu_ids,
98 .priv_auto_alloc_size = sizeof(struct ccu_priv),
99 .ops = &sunxi_clk_ops,
100 .probe = sunxi_clk_probe,
101 .bind = h6_clk_bind,
102};