| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ |
| 2 | /* |
| 3 | * Copyright (C) 2021 Ahmad Fatoum, Pengutronix |
| 4 | */ |
| 5 | |
| 6 | #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ |
| 7 | #define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ |
| 8 | |
| 9 | #define JH7100_RSTN_DOM3AHB_BUS 0 |
| 10 | #define JH7100_RSTN_DOM7AHB_BUS 1 |
| 11 | #define JH7100_RST_U74 2 |
| 12 | #define JH7100_RSTN_U74_AXI 3 |
| 13 | #define JH7100_RSTN_SGDMA2P_AHB 4 |
| 14 | #define JH7100_RSTN_SGDMA2P_AXI 5 |
| 15 | #define JH7100_RSTN_DMA2PNOC_AXI 6 |
| 16 | #define JH7100_RSTN_DLA_AXI 7 |
| 17 | #define JH7100_RSTN_DLANOC_AXI 8 |
| 18 | #define JH7100_RSTN_DLA_APB 9 |
| 19 | #define JH7100_RST_VP6_DRESET 10 |
| 20 | #define JH7100_RST_VP6_BRESET 11 |
| 21 | #define JH7100_RSTN_VP6_AXI 12 |
| 22 | #define JH7100_RSTN_VDECBRG_MAIN 13 |
| 23 | #define JH7100_RSTN_VDEC_AXI 14 |
| 24 | #define JH7100_RSTN_VDEC_BCLK 15 |
| 25 | #define JH7100_RSTN_VDEC_CCLK 16 |
| 26 | #define JH7100_RSTN_VDEC_APB 17 |
| 27 | #define JH7100_RSTN_JPEG_AXI 18 |
| 28 | #define JH7100_RSTN_JPEG_CCLK 19 |
| 29 | #define JH7100_RSTN_JPEG_APB 20 |
| 30 | #define JH7100_RSTN_JPCGC300_MAIN 21 |
| 31 | #define JH7100_RSTN_GC300_2X 22 |
| 32 | #define JH7100_RSTN_GC300_AXI 23 |
| 33 | #define JH7100_RSTN_GC300_AHB 24 |
| 34 | #define JH7100_RSTN_VENC_AXI 25 |
| 35 | #define JH7100_RSTN_VENCBRG_MAIN 26 |
| 36 | #define JH7100_RSTN_VENC_BCLK 27 |
| 37 | #define JH7100_RSTN_VENC_CCLK 28 |
| 38 | #define JH7100_RSTN_VENC_APB 29 |
| 39 | #define JH7100_RSTN_DDRPHY_APB 30 |
| 40 | #define JH7100_RSTN_NOC_ROB 31 |
| 41 | #define JH7100_RSTN_NOC_COG 32 |
| 42 | #define JH7100_RSTN_HIFI4_AXI 33 |
| 43 | #define JH7100_RSTN_HIFI4NOC_AXI 34 |
| 44 | #define JH7100_RST_HIFI4_DRESET 35 |
| 45 | #define JH7100_RST_HIFI4_BRESET 36 |
| 46 | #define JH7100_RSTN_USB_AXI 37 |
| 47 | #define JH7100_RSTN_USBNOC_AXI 38 |
| 48 | #define JH7100_RSTN_SGDMA1P_AXI 39 |
| 49 | #define JH7100_RSTN_DMA1P_AXI 40 |
| 50 | #define JH7100_RSTN_X2C_AXI 41 |
| 51 | #define JH7100_RSTN_NNE_AHB 42 |
| 52 | #define JH7100_RSTN_NNE_AXI 43 |
| 53 | #define JH7100_RSTN_NNENOC_AXI 44 |
| 54 | #define JH7100_RSTN_DLASLV_AXI 45 |
| 55 | #define JH7100_RSTN_DSPX2C_AXI 46 |
| 56 | #define JH7100_RSTN_VIN_SRC 47 |
| 57 | #define JH7100_RSTN_ISPSLV_AXI 48 |
| 58 | #define JH7100_RSTN_VIN_AXI 49 |
| 59 | #define JH7100_RSTN_VINNOC_AXI 50 |
| 60 | #define JH7100_RSTN_ISP0_AXI 51 |
| 61 | #define JH7100_RSTN_ISP0NOC_AXI 52 |
| 62 | #define JH7100_RSTN_ISP1_AXI 53 |
| 63 | #define JH7100_RSTN_ISP1NOC_AXI 54 |
| 64 | #define JH7100_RSTN_VOUT_SRC 55 |
| 65 | #define JH7100_RSTN_DISP_AXI 56 |
| 66 | #define JH7100_RSTN_DISPNOC_AXI 57 |
| 67 | #define JH7100_RSTN_SDIO0_AHB 58 |
| 68 | #define JH7100_RSTN_SDIO1_AHB 59 |
| 69 | #define JH7100_RSTN_GMAC_AHB 60 |
| 70 | #define JH7100_RSTN_SPI2AHB_AHB 61 |
| 71 | #define JH7100_RSTN_SPI2AHB_CORE 62 |
| 72 | #define JH7100_RSTN_EZMASTER_AHB 63 |
| 73 | #define JH7100_RST_E24 64 |
| 74 | #define JH7100_RSTN_QSPI_AHB 65 |
| 75 | #define JH7100_RSTN_QSPI_CORE 66 |
| 76 | #define JH7100_RSTN_QSPI_APB 67 |
| 77 | #define JH7100_RSTN_SEC_AHB 68 |
| 78 | #define JH7100_RSTN_AES 69 |
| 79 | #define JH7100_RSTN_PKA 70 |
| 80 | #define JH7100_RSTN_SHA 71 |
| 81 | #define JH7100_RSTN_TRNG_APB 72 |
| 82 | #define JH7100_RSTN_OTP_APB 73 |
| 83 | #define JH7100_RSTN_UART0_APB 74 |
| 84 | #define JH7100_RSTN_UART0_CORE 75 |
| 85 | #define JH7100_RSTN_UART1_APB 76 |
| 86 | #define JH7100_RSTN_UART1_CORE 77 |
| 87 | #define JH7100_RSTN_SPI0_APB 78 |
| 88 | #define JH7100_RSTN_SPI0_CORE 79 |
| 89 | #define JH7100_RSTN_SPI1_APB 80 |
| 90 | #define JH7100_RSTN_SPI1_CORE 81 |
| 91 | #define JH7100_RSTN_I2C0_APB 82 |
| 92 | #define JH7100_RSTN_I2C0_CORE 83 |
| 93 | #define JH7100_RSTN_I2C1_APB 84 |
| 94 | #define JH7100_RSTN_I2C1_CORE 85 |
| 95 | #define JH7100_RSTN_GPIO_APB 86 |
| 96 | #define JH7100_RSTN_UART2_APB 87 |
| 97 | #define JH7100_RSTN_UART2_CORE 88 |
| 98 | #define JH7100_RSTN_UART3_APB 89 |
| 99 | #define JH7100_RSTN_UART3_CORE 90 |
| 100 | #define JH7100_RSTN_SPI2_APB 91 |
| 101 | #define JH7100_RSTN_SPI2_CORE 92 |
| 102 | #define JH7100_RSTN_SPI3_APB 93 |
| 103 | #define JH7100_RSTN_SPI3_CORE 94 |
| 104 | #define JH7100_RSTN_I2C2_APB 95 |
| 105 | #define JH7100_RSTN_I2C2_CORE 96 |
| 106 | #define JH7100_RSTN_I2C3_APB 97 |
| 107 | #define JH7100_RSTN_I2C3_CORE 98 |
| 108 | #define JH7100_RSTN_WDTIMER_APB 99 |
| 109 | #define JH7100_RSTN_WDT 100 |
| 110 | #define JH7100_RSTN_TIMER0 101 |
| 111 | #define JH7100_RSTN_TIMER1 102 |
| 112 | #define JH7100_RSTN_TIMER2 103 |
| 113 | #define JH7100_RSTN_TIMER3 104 |
| 114 | #define JH7100_RSTN_TIMER4 105 |
| 115 | #define JH7100_RSTN_TIMER5 106 |
| 116 | #define JH7100_RSTN_TIMER6 107 |
| 117 | #define JH7100_RSTN_VP6INTC_APB 108 |
| 118 | #define JH7100_RSTN_PWM_APB 109 |
| 119 | #define JH7100_RSTN_MSI_APB 110 |
| 120 | #define JH7100_RSTN_TEMP_APB 111 |
| 121 | #define JH7100_RSTN_TEMP_SENSE 112 |
| 122 | #define JH7100_RSTN_SYSERR_APB 113 |
| 123 | |
| 124 | #define JH7100_RSTN_END 114 |
| 125 | |
| 126 | #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */ |