| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> |
| 4 | * Copyright (c) 2020 Western Digital Corporation or its affiliates. |
| 5 | */ |
| 6 | #ifndef RESET_K210_SYSCTL_H |
| 7 | #define RESET_K210_SYSCTL_H |
| 8 | |
| 9 | /* |
| 10 | * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. |
| 11 | * Taken from Kendryte SDK (kendryte-standalone-sdk). |
| 12 | */ |
| 13 | #define K210_RST_ROM 0 |
| 14 | #define K210_RST_DMA 1 |
| 15 | #define K210_RST_AI 2 |
| 16 | #define K210_RST_DVP 3 |
| 17 | #define K210_RST_FFT 4 |
| 18 | #define K210_RST_GPIO 5 |
| 19 | #define K210_RST_SPI0 6 |
| 20 | #define K210_RST_SPI1 7 |
| 21 | #define K210_RST_SPI2 8 |
| 22 | #define K210_RST_SPI3 9 |
| 23 | #define K210_RST_I2S0 10 |
| 24 | #define K210_RST_I2S1 11 |
| 25 | #define K210_RST_I2S2 12 |
| 26 | #define K210_RST_I2C0 13 |
| 27 | #define K210_RST_I2C1 14 |
| 28 | #define K210_RST_I2C2 15 |
| 29 | #define K210_RST_UART1 16 |
| 30 | #define K210_RST_UART2 17 |
| 31 | #define K210_RST_UART3 18 |
| 32 | #define K210_RST_AES 19 |
| 33 | #define K210_RST_FPIOA 20 |
| 34 | #define K210_RST_TIMER0 21 |
| 35 | #define K210_RST_TIMER1 22 |
| 36 | #define K210_RST_TIMER2 23 |
| 37 | #define K210_RST_WDT0 24 |
| 38 | #define K210_RST_WDT1 25 |
| 39 | #define K210_RST_SHA 26 |
| 40 | #define K210_RST_RTC 29 |
| 41 | |
| 42 | #endif /* RESET_K210_SYSCTL_H */ |