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git01.mediatek.com / filogic / uboot / 532c0b5ee9491e7212a6619cb6dfc685b3987be2 / . / configs / C29XPCIE_NOR_SECBOOT_defconfig
blob: e43c72860a03f744b1433940aa4e5337cc1b45e8 [file] [log] [blame]
Po Liu500b9452014-11-26 09:38:48 +0800[diff] [blame]1CONFIG_PPC=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]2CONFIG_SYS_TEXT_BASE=0xEFF40000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]3CONFIG_ENV_SIZE=0x2000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]4CONFIG_NXP_ESBC=y
Po Liu500b9452014-11-26 09:38:48 +0800[diff] [blame]5CONFIG_MPC85xx=y
6CONFIG_TARGET_C29XPCIE=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]7# CONFIG_SYS_MALLOC_F is not set
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]8CONFIG_FIT=y
9CONFIG_FIT_VERBOSE=y
10CONFIG_OF_BOARD_SETUP=y
11CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rinib937b2e2016-06-13 09:45:14 -0400[diff] [blame]12CONFIG_BOOTDELAY=-1
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]13CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Adam Ford10541762018-07-29 13:13:29 -0500[diff] [blame]14# CONFIG_MISC_INIT_R is not set
Mario Six75b23ed2018-03-28 14:38:15 +0200[diff] [blame]15CONFIG_BOARD_EARLY_INIT_R=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]16CONFIG_HUSH_PARSER=y
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]17CONFIG_CMD_IMLS=y
Simon Glass4590d4e2017-05-17 03:25:10 -0600[diff] [blame]18CONFIG_CMD_EEPROM=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]19CONFIG_CMD_I2C=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]20CONFIG_CMD_SF=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]21CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]22CONFIG_CMD_PING=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]23CONFIG_DOS_PARTITION=y
Simon Glassd9b4d052016-02-22 22:55:41 -0700[diff] [blame]24CONFIG_DM=y
Jagan Teki4c57e4c2017-01-21 11:48:33 +0100[diff] [blame]25# CONFIG_MMC is not set
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]26CONFIG_MTD=y
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]27CONFIG_MTD_NOR_FLASH=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]28CONFIG_FLASH_CFI_DRIVER=y
29CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
30CONFIG_SYS_FLASH_CFI=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]31CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]32CONFIG_SF_DEFAULT_MODE=0
33CONFIG_SF_DEFAULT_SPEED=10000000
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]34CONFIG_SPI_FLASH_EON=y
35CONFIG_SPI_FLASH_SPANSION=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]36CONFIG_PHY_ATHEROS=y
37CONFIG_PHY_BROADCOM=y
38CONFIG_PHY_DAVICOM=y
39CONFIG_PHY_LXT=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]40CONFIG_PHY_MARVELL=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]41CONFIG_PHY_NATSEMI=y
42CONFIG_PHY_REALTEK=y
43CONFIG_PHY_SMSC=y
44CONFIG_PHY_VITESSE=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]45CONFIG_PHY_GIGE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]46CONFIG_E1000=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]47CONFIG_MII=y
Mario Sixda4fc932018-03-28 14:38:18 +0200[diff] [blame]48CONFIG_TSEC_ENET=y
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]49CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]50CONFIG_SPI=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]51CONFIG_FSL_ESPI=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]52CONFIG_RSA=y
Simon Glass73ad4d02016-09-12 23:18:29 -0600[diff] [blame]53CONFIG_SPL_RSA=y
Tom Rinia5c4d402017-03-01 16:51:58 -0500[diff] [blame]54CONFIG_RSA_SOFTWARE_EXP=y
Simon Glassa66c5412016-02-22 22:55:42 -0700[diff] [blame]55CONFIG_OF_LIBFDT=y