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wdenkfe8c2802002-11-03 00:38:21 +00001/*
Wolfgang Denkc80857e2006-07-21 11:56:05 +02002 * (C) Copyright 2000-2006
wdenkfe8c2802002-11-03 00:38:21 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Stefan Roese3ddce572010-09-20 16:05:31 +02005 * (C) Copyright 2010
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +00009 */
Stefan Roese1a471152007-10-22 16:22:40 +020010
wdenkfe8c2802002-11-03 00:38:21 +000011/*
Josh Boyer471573b2009-08-07 13:53:20 -040012 * This source code is dual-licensed. You may use it under the terms of the
13 * GNU General Public License version 2, or under the license below.
14 *
wdenkfe8c2802002-11-03 00:38:21 +000015 * This source code has been made available to you by IBM on an AS-IS
16 * basis. Anyone receiving this source is licensed under IBM
17 * copyrights to use it in any way he or she deems fit, including
18 * copying it, modifying it, compiling it, and redistributing it either
19 * with or without modifications. No license under IBM patents or
20 * patent applications is to be implied by the copyright license.
21 *
22 * Any user of this software should understand that IBM cannot provide
23 * technical support for this software and will not be responsible for
24 * any consequences resulting from the use of this software.
25 *
26 * Any person who transfers this source code or any derivative work
27 * must include the IBM copyright notice, this paragraph, and the
28 * preceding two paragraphs in the transferred software.
29 *
30 * COPYRIGHT I B M CORPORATION 1995
31 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
32 */
Stefan Roese1a471152007-10-22 16:22:40 +020033
wdenkfe8c2802002-11-03 00:38:21 +000034#include <common.h>
35#include <commproc.h>
36#include <asm/processor.h>
Stefan Roese1a471152007-10-22 16:22:40 +020037#include <asm/io.h>
wdenkfe8c2802002-11-03 00:38:21 +000038#include <watchdog.h>
Stefan Roese247e9d72010-09-09 19:18:00 +020039#include <asm/ppc4xx.h>
wdenkfe8c2802002-11-03 00:38:21 +000040
Wolfgang Denk6405a152006-03-31 18:32:53 +020041DECLARE_GLOBAL_DATA_PTR;
42
Stefan Roese17ffbc82007-03-21 13:38:59 +010043#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
44 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
Stefan Roese153b3e22007-10-05 17:10:59 +020045 defined(CONFIG_405EX) || defined(CONFIG_440)
wdenkfe8c2802002-11-03 00:38:21 +000046
47#if defined(CONFIG_440)
Stefan Roesebdd13d12008-03-11 15:05:26 +010048
Stefan Roese42fbddd2006-09-07 11:51:23 +020049#if defined(CONFIG_440GP)
wdenkfe8c2802002-11-03 00:38:21 +000050#define CR0_MASK 0x3fff0000
51#define CR0_EXTCLK_ENA 0x00600000
52#define CR0_UDIV_POS 16
Stefan Roese42fbddd2006-09-07 11:51:23 +020053#define UDIV_SUBTRACT 1
Stefan Roese918010a2009-09-09 16:25:29 +020054#define UART0_SDR CPC0_CR0
Stefan Roese42fbddd2006-09-07 11:51:23 +020055#define MFREG(a, d) d = mfdcr(a)
56#define MTREG(a, d) mtdcr(a, d)
57#else /* #if defined(CONFIG_440GP) */
58/* all other 440 PPC's access clock divider via sdr register */
59#define CR0_MASK 0xdfffffff
60#define CR0_EXTCLK_ENA 0x00800000
61#define CR0_UDIV_POS 0
62#define UDIV_SUBTRACT 0
Stefan Roese918010a2009-09-09 16:25:29 +020063#define UART0_SDR SDR0_UART0
64#define UART1_SDR SDR0_UART1
Stefan Roese422853e2008-06-06 16:10:41 +020065#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
66 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
67 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roesebdd13d12008-03-11 15:05:26 +010068 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese918010a2009-09-09 16:25:29 +020069#define UART2_SDR SDR0_UART2
Stefan Roese42fbddd2006-09-07 11:51:23 +020070#endif
Stefan Roese422853e2008-06-06 16:10:41 +020071#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
72 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
Stefan Roesebdd13d12008-03-11 15:05:26 +010073 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese918010a2009-09-09 16:25:29 +020074#define UART3_SDR SDR0_UART3
Stefan Roese42fbddd2006-09-07 11:51:23 +020075#endif
76#define MFREG(a, d) mfsdr(a, d)
77#define MTREG(a, d) mtsdr(a, d)
78#endif /* #if defined(CONFIG_440GP) */
Stefan Roese17ffbc82007-03-21 13:38:59 +010079#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
stroese937d6672003-05-23 11:25:57 +000080#define UCR0_MASK 0x0000007f
81#define UCR1_MASK 0x00007f00
82#define UCR0_UDIV_POS 0
83#define UCR1_UDIV_POS 8
84#define UDIV_MAX 127
Stefan Roese153b3e22007-10-05 17:10:59 +020085#elif defined(CONFIG_405EX)
Stefan Roese3ddce572010-09-20 16:05:31 +020086#define MFREG(a, d) mfsdr(a, d)
87#define MTREG(a, d) mtsdr(a, d)
Stefan Roese153b3e22007-10-05 17:10:59 +020088#define CR0_MASK 0x000000ff
89#define CR0_EXTCLK_ENA 0x00800000
90#define CR0_UDIV_POS 0
91#define UDIV_SUBTRACT 0
Stefan Roese918010a2009-09-09 16:25:29 +020092#define UART0_SDR SDR0_UART0
93#define UART1_SDR SDR0_UART1
stroese937d6672003-05-23 11:25:57 +000094#else /* CONFIG_405GP || CONFIG_405CR */
wdenkfe8c2802002-11-03 00:38:21 +000095#define CR0_MASK 0x00001fff
stroese85d0fec2003-02-17 16:06:06 +000096#define CR0_EXTCLK_ENA 0x000000c0
wdenkfe8c2802002-11-03 00:38:21 +000097#define CR0_UDIV_POS 1
stroese937d6672003-05-23 11:25:57 +000098#define UDIV_MAX 32
99#endif
100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
Wolfgang Denk0ee70772005-09-23 11:05:55 +0200102#error "External serial clock not supported on AMCC PPC405EP!"
wdenkfe8c2802002-11-03 00:38:21 +0000103#endif
104
Stefan Roese3ddce572010-09-20 16:05:31 +0200105#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
106 defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
107/*
108 * For some SoC's, the cpu clock is on divider chain A, UART on
109 * divider chain B ... so cpu clock is irrelevant. Get the
110 * "optimized" values that are subject to the 1/2 opb clock
111 * constraint.
112 */
113static u16 serial_bdiv(int baudrate, u32 *udiv)
wdenkfe8c2802002-11-03 00:38:21 +0000114{
Stefan Roese17ffbc82007-03-21 13:38:59 +0100115 sys_info_t sysinfo;
Stefan Roese3ddce572010-09-20 16:05:31 +0200116 u32 div; /* total divisor udiv * bdiv */
117 u32 umin; /* minimum udiv */
118 u16 diff; /* smallest diff */
119 u16 idiff; /* current diff */
120 u16 ibdiv; /* current bdiv */
121 u32 i;
122 u32 est; /* current estimate */
123 u32 max;
124#if defined(CONFIG_405EZ)
125 u32 cpr_pllc;
126 u32 plloutb;
127 u32 reg;
128#endif
wdenkfe8c2802002-11-03 00:38:21 +0000129
Stefan Roese17ffbc82007-03-21 13:38:59 +0100130 get_sys_info(&sysinfo);
wdenkfe8c2802002-11-03 00:38:21 +0000131
Stefan Roese3ddce572010-09-20 16:05:31 +0200132#if defined(CONFIG_405EZ)
Stefan Roese87476ba2007-08-13 09:05:33 +0200133 /* check the pll feedback source */
Stefan Roese918010a2009-09-09 16:25:29 +0200134 mfcpr(CPR0_PLLC, cpr_pllc);
Stefan Roese3dae28e2007-08-14 15:03:17 +0200135 plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
Stefan Roese1a471152007-10-22 16:22:40 +0200136 sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
137 sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
Stefan Roese17ffbc82007-03-21 13:38:59 +0100138 div = plloutb / (16 * baudrate); /* total divisor */
139 umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
Stefan Roese3ddce572010-09-20 16:05:31 +0200140 max = 256; /* highest possible */
141#else /* 405EZ */
142 div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
143 umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
144 max = 32; /* highest possible */
145#endif /* 405EZ */
146
147 *udiv = diff = max;
Stefan Roese17ffbc82007-03-21 13:38:59 +0100148
Stefan Roese3ddce572010-09-20 16:05:31 +0200149 /*
150 * i is the test udiv value -- start with the largest
151 * possible (max) to minimize serial clock and constrain
Stefan Roese17ffbc82007-03-21 13:38:59 +0100152 * search to umin.
153 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200154 for (i = max; i > umin; i--) {
Stefan Roese17ffbc82007-03-21 13:38:59 +0100155 ibdiv = div / i;
156 est = i * ibdiv;
Stefan Roese3ddce572010-09-20 16:05:31 +0200157 idiff = (est > div) ? (est - div) : (div - est);
Stefan Roese17ffbc82007-03-21 13:38:59 +0100158 if (idiff == 0) {
Stefan Roese3ddce572010-09-20 16:05:31 +0200159 *udiv = i;
160 break; /* can't do better */
Stefan Roese17ffbc82007-03-21 13:38:59 +0100161 } else if (idiff < diff) {
Stefan Roese3ddce572010-09-20 16:05:31 +0200162 *udiv = i; /* best so far */
163 diff = idiff; /* update lowest diff*/
Stefan Roese17ffbc82007-03-21 13:38:59 +0100164 }
165 }
166
Stefan Roese3ddce572010-09-20 16:05:31 +0200167#if defined(CONFIG_405EZ)
Stefan Roese8cb251a2010-09-12 06:21:37 +0200168 mfcpr(CPR0_PERD0, reg);
Stefan Roese17ffbc82007-03-21 13:38:59 +0100169 reg &= ~0x0000ffff;
Stefan Roese3ddce572010-09-20 16:05:31 +0200170 reg |= ((*udiv - 0) << 8) | (*udiv - 0);
Stefan Roese8cb251a2010-09-12 06:21:37 +0200171 mtcpr(CPR0_PERD0, reg);
Stefan Roese3ddce572010-09-20 16:05:31 +0200172#endif
173
174 return div / *udiv;
wdenkfe8c2802002-11-03 00:38:21 +0000175}
Stefan Roese3ddce572010-09-20 16:05:31 +0200176#endif /* #if (defined(CONFIG_405EP) ... */
wdenkfe8c2802002-11-03 00:38:21 +0000177
wdenkfe8c2802002-11-03 00:38:21 +0000178/*
Stefan Roese3ddce572010-09-20 16:05:31 +0200179 * This function returns the UART clock used by the common
180 * NS16550 driver. Additionally the SoC internal divisors for
181 * optimal UART baudrate are configured.
wdenkfe8c2802002-11-03 00:38:21 +0000182 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200183int get_serial_clock(void)
wdenkfe8c2802002-11-03 00:38:21 +0000184{
Stefan Roese3ddce572010-09-20 16:05:31 +0200185 u32 clk;
186 u32 udiv;
Stefan Roese3ddce572010-09-20 16:05:31 +0200187#if !defined(CONFIG_405EZ)
188 u32 reg;
wdenk96c7a8c2005-01-09 22:28:56 +0000189#endif
Stefan Roese3ddce572010-09-20 16:05:31 +0200190#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
191 PPC4xx_SYS_INFO sys_info;
Stefan Roese153b3e22007-10-05 17:10:59 +0200192#endif
Stefan Roese153b3e22007-10-05 17:10:59 +0200193
194 /*
Stefan Roese3ddce572010-09-20 16:05:31 +0200195 * Programming of the internal divisors is SoC specific.
196 * Let's handle this in some #ifdef's for the SoC's.
Stefan Roese153b3e22007-10-05 17:10:59 +0200197 */
Stefan Roese153b3e22007-10-05 17:10:59 +0200198
Stefan Roese3ddce572010-09-20 16:05:31 +0200199#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
Stefan Roese918010a2009-09-09 16:25:29 +0200200 reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200201#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
202 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
wdenkfe8c2802002-11-03 00:38:21 +0000203 udiv = 1;
204 reg |= CR0_EXTCLK_ENA;
Stefan Roese3ddce572010-09-20 16:05:31 +0200205#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
wdenkfe8c2802002-11-03 00:38:21 +0000206 clk = gd->cpu_clk;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#ifdef CONFIG_SYS_405_UART_ERRATA_59
wdenkfe8c2802002-11-03 00:38:21 +0000208 udiv = 31; /* Errata 59: stuck at 31 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200209#else /* CONFIG_SYS_405_UART_ERRATA_59 */
Wolfgang Denkdf592922011-10-29 09:37:52 +0000210 {
211 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
212
213 udiv = (clk + tmp / 2) / tmp;
214 }
stroese937d6672003-05-23 11:25:57 +0000215 if (udiv > UDIV_MAX) /* max. n bits for udiv */
216 udiv = UDIV_MAX;
Stefan Roese3ddce572010-09-20 16:05:31 +0200217#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
218#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
wdenkfe8c2802002-11-03 00:38:21 +0000219 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
Stefan Roese918010a2009-09-09 16:25:29 +0200220 mtdcr (CPC0_CR0, reg);
Stefan Roese3ddce572010-09-20 16:05:31 +0200221#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
222 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
wdenkfe8c2802002-11-03 00:38:21 +0000223#else
Stefan Roese3ddce572010-09-20 16:05:31 +0200224 clk = CONFIG_SYS_BASE_BAUD * 16;
wdenkfe8c2802002-11-03 00:38:21 +0000225#endif
Stefan Roese3ddce572010-09-20 16:05:31 +0200226#endif /* CONFIG_405CR */
wdenkfe8c2802002-11-03 00:38:21 +0000227
Stefan Roese3ddce572010-09-20 16:05:31 +0200228#if defined(CONFIG_405EP)
Wolfgang Denkdf592922011-10-29 09:37:52 +0000229 {
230 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
231
232 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
233 clk = gd->cpu_clk;
234 udiv = (clk + tmp / 2) / tmp;
235 if (udiv > UDIV_MAX) /* max. n bits for udiv */
236 udiv = UDIV_MAX;
237 }
Stefan Roese3ddce572010-09-20 16:05:31 +0200238 reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
239 reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
240 mtdcr(CPC0_UCR, reg);
241 clk = CONFIG_SYS_BASE_BAUD * 16;
242#endif /* CONFIG_405EP */
wdenkfe8c2802002-11-03 00:38:21 +0000243
Stefan Roese3ddce572010-09-20 16:05:31 +0200244#if defined(CONFIG_405EX) || defined(CONFIG_440)
245 MFREG(UART0_SDR, reg);
246 reg &= ~CR0_MASK;
wdenkfe8c2802002-11-03 00:38:21 +0000247
Stefan Roese3ddce572010-09-20 16:05:31 +0200248#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
249 reg |= CR0_EXTCLK_ENA;
250 udiv = 1;
251 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
252#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
253 clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
254#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
wdenkfe8c2802002-11-03 00:38:21 +0000255
Stefan Roese3ddce572010-09-20 16:05:31 +0200256 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
wdenkfe8c2802002-11-03 00:38:21 +0000257
wdenkfe8c2802002-11-03 00:38:21 +0000258 /*
Stefan Roese3ddce572010-09-20 16:05:31 +0200259 * Configure input clock to baudrate generator for all
260 * available serial ports here
wdenkfe8c2802002-11-03 00:38:21 +0000261 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200262 MTREG(UART0_SDR, reg);
263#if defined(UART1_SDR)
264 MTREG(UART1_SDR, reg);
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500265#endif
Stefan Roese3ddce572010-09-20 16:05:31 +0200266#if defined(UART2_SDR)
267 MTREG(UART2_SDR, reg);
268#endif
269#if defined(UART3_SDR)
270 MTREG(UART3_SDR, reg);
271#endif
272#endif /* CONFIG_405EX ... */
wdenk96c7a8c2005-01-09 22:28:56 +0000273
Stefan Roese3ddce572010-09-20 16:05:31 +0200274#if defined(CONFIG_405EZ)
275 clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
276#endif /* CONFIG_405EZ */
wdenk96c7a8c2005-01-09 22:28:56 +0000277
Stefan Roese3ddce572010-09-20 16:05:31 +0200278 /*
279 * Correct UART frequency in bd-info struct now that
280 * the UART divisor is available
281 */
282#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
Simon Glass004cc852012-12-13 20:48:59 +0000283 gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
Stefan Roese1a471152007-10-22 16:22:40 +0200284#else
Stefan Roese3ddce572010-09-20 16:05:31 +0200285 get_sys_info(&sys_info);
Simon Glass004cc852012-12-13 20:48:59 +0000286 gd->arch.uart_clk = sys_info.freqUART / udiv;
Stefan Roese3ddce572010-09-20 16:05:31 +0200287#endif
Stefan Roese1a471152007-10-22 16:22:40 +0200288
Stefan Roese3ddce572010-09-20 16:05:31 +0200289 return clk;
Stefan Roese1a471152007-10-22 16:22:40 +0200290}
wdenkfe8c2802002-11-03 00:38:21 +0000291#endif /* CONFIG_405GP || CONFIG_405CR */