blob: 5d8f21059f6731f7c822affa2b462ab0955c04c1 [file] [log] [blame]
Stephen Warren24bfee62012-05-21 10:04:37 +00001/dts-v1/;
2
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +03003#include <dt-bindings/input/input.h>
Tom Warrenf6236152013-02-21 12:31:27 +00004#include "tegra20.dtsi"
Stephen Warren24bfee62012-05-21 10:04:37 +00005
6/ {
Tom Warrened955272013-02-21 12:31:29 +00007 model = "Toshiba AC100 / Dynabook AZ";
8 compatible = "compal,paz00", "nvidia,tegra20";
Stephen Warren24bfee62012-05-21 10:04:37 +00009
Simon Glass0c24f372014-09-04 16:27:35 -060010 chosen {
11 stdout-path = &uarta;
12 };
13
Stephen Warren24bfee62012-05-21 10:04:37 +000014 aliases {
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +030015 rtc0 = "/i2c@7000d000/tps6586x@34";
16 rtc1 = "/rtc@7000e000";
17 serial0 = &uarta;
18 serial1 = &uartc;
19 usb0 = "/usb@c5000000";
20 usb1 = "/usb@c5004000";
21 usb2 = "/usb@c5008000";
Stephen Warrend55aadc2016-09-13 10:45:43 -060022 mmc0 = "/sdhci@c8000600";
23 mmc1 = "/sdhci@c8000000";
Stephen Warren24bfee62012-05-21 10:04:37 +000024 };
25
26 memory {
27 reg = <0x00000000 0x20000000>;
28 };
29
Simon Glasse31a2a52016-01-30 16:37:52 -070030 host1x@50000000 {
Allen Martin0398dcb2013-01-16 13:12:24 +000031 status = "okay";
32 dc@54200000 {
33 status = "okay";
34 rgb {
35 status = "okay";
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +030036
37 nvidia,panel = <&panel>;
38
39 display-timings {
40 timing@0 {
41 /* PAZ00 has 1024x600 */
42 clock-frequency = <54030000>;
43 hactive = <1024>;
44 vactive = <600>;
45 hback-porch = <160>;
46 hfront-porch = <24>;
47 hsync-len = <136>;
48 vback-porch = <3>;
49 vfront-porch = <61>;
50 vsync-len = <6>;
51 hsync-active = <1>;
52 };
53 };
54 };
55 };
56
57 hdmi@54280000 {
58 status = "okay";
59
60 vdd-supply = <&hdmi_vdd_reg>;
61 pll-supply = <&hdmi_pll_reg>;
62
63 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
64 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
65 GPIO_ACTIVE_HIGH>;
66 };
67 };
68
69 pinmux@70000014 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&state_default>;
72
73 state_default: pinmux {
74 ata {
75 nvidia,pins = "ata", "atc", "atd", "ate",
76 "dap2", "gmb", "gmc", "gmd", "spia",
77 "spib", "spic", "spid", "spie";
78 nvidia,function = "gmi";
79 };
80 atb {
81 nvidia,pins = "atb", "gma", "gme";
82 nvidia,function = "sdio4";
83 };
84 cdev1 {
85 nvidia,pins = "cdev1";
86 nvidia,function = "plla_out";
87 };
88 cdev2 {
89 nvidia,pins = "cdev2";
90 nvidia,function = "pllp_out4";
91 };
92 crtp {
93 nvidia,pins = "crtp";
94 nvidia,function = "crt";
95 };
96 csus {
97 nvidia,pins = "csus";
98 nvidia,function = "pllc_out1";
99 };
100 dap1 {
101 nvidia,pins = "dap1";
102 nvidia,function = "dap1";
103 };
104 dap3 {
105 nvidia,pins = "dap3";
106 nvidia,function = "dap3";
107 };
108 dap4 {
109 nvidia,pins = "dap4";
110 nvidia,function = "dap4";
111 };
112 ddc {
113 nvidia,pins = "ddc";
114 nvidia,function = "i2c2";
115 };
116 dta {
117 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
118 nvidia,function = "rsvd1";
119 };
120 dtf {
121 nvidia,pins = "dtf";
122 nvidia,function = "i2c3";
123 };
124 gpu {
125 nvidia,pins = "gpu", "sdb", "sdd";
126 nvidia,function = "pwm";
127 };
128 gpu7 {
129 nvidia,pins = "gpu7";
130 nvidia,function = "rtck";
131 };
132 gpv {
133 nvidia,pins = "gpv", "slxa", "slxk";
134 nvidia,function = "pcie";
135 };
136 hdint {
137 nvidia,pins = "hdint", "pta";
138 nvidia,function = "hdmi";
139 };
140 i2cp {
141 nvidia,pins = "i2cp";
142 nvidia,function = "i2cp";
143 };
144 irrx {
145 nvidia,pins = "irrx", "irtx";
146 nvidia,function = "uarta";
147 };
148 kbca {
149 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
150 nvidia,function = "kbc";
151 };
152 kbcb {
153 nvidia,pins = "kbcb", "kbcd";
154 nvidia,function = "sdio2";
155 };
156 lcsn {
157 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
158 "ld3", "ld4", "ld5", "ld6", "ld7",
159 "ld8", "ld9", "ld10", "ld11", "ld12",
160 "ld13", "ld14", "ld15", "ld16", "ld17",
161 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
162 "lhs", "lm0", "lm1", "lpp", "lpw0",
163 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
164 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
165 "lvs";
166 nvidia,function = "displaya";
167 };
168 owc {
169 nvidia,pins = "owc";
170 nvidia,function = "owr";
171 };
172 pmc {
173 nvidia,pins = "pmc";
174 nvidia,function = "pwr_on";
175 };
176 rm {
177 nvidia,pins = "rm";
178 nvidia,function = "i2c1";
179 };
180 sdc {
181 nvidia,pins = "sdc";
182 nvidia,function = "twc";
183 };
184 sdio1 {
185 nvidia,pins = "sdio1";
186 nvidia,function = "sdio1";
187 };
188 slxc {
189 nvidia,pins = "slxc", "slxd";
190 nvidia,function = "spi4";
191 };
192 spdi {
193 nvidia,pins = "spdi", "spdo";
194 nvidia,function = "rsvd2";
195 };
196 spif {
197 nvidia,pins = "spif", "uac";
198 nvidia,function = "rsvd4";
199 };
200 spig {
201 nvidia,pins = "spig", "spih";
202 nvidia,function = "spi2_alt";
203 };
204 uaa {
205 nvidia,pins = "uaa", "uab", "uda";
206 nvidia,function = "ulpi";
207 };
208 uad {
209 nvidia,pins = "uad";
210 nvidia,function = "spdif";
211 };
212 uca {
213 nvidia,pins = "uca", "ucb";
214 nvidia,function = "uartc";
215 };
216 conf_ata {
217 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
218 "cdev1", "cdev2", "dap1", "dap2", "dtf",
219 "gma", "gmb", "gmc", "gmd", "gme",
220 "gpu", "gpu7", "gpv", "i2cp", "pta",
221 "rm", "sdio1", "slxk", "spdo", "uac",
222 "uda";
223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224 nvidia,tristate = <TEGRA_PIN_DISABLE>;
225 };
226 conf_ck32 {
227 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
228 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
229 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
230 };
231 conf_crtp {
232 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
233 "dtc", "dte", "slxa", "slxc", "slxd",
234 "spdi";
235 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
236 nvidia,tristate = <TEGRA_PIN_ENABLE>;
237 };
238 conf_csus {
239 nvidia,pins = "csus", "spia", "spib", "spid",
240 "spif";
241 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
242 nvidia,tristate = <TEGRA_PIN_ENABLE>;
243 };
244 conf_ddc {
245 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
246 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
247 "spic", "spig", "uaa", "uab";
248 nvidia,pull = <TEGRA_PIN_PULL_UP>;
249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
250 };
251 conf_dta {
252 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
253 "spie", "spih", "uad", "uca", "ucb";
254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
255 nvidia,tristate = <TEGRA_PIN_ENABLE>;
256 };
257 conf_hdint {
258 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
259 "ld3", "ld4", "ld5", "ld6", "ld7",
260 "ld8", "ld9", "ld10", "ld11", "ld12",
261 "ld13", "ld14", "ld15", "ld16", "ld17",
262 "ldc", "ldi", "lhs", "lsc0", "lspi",
263 "lvs", "pmc";
264 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265 };
266 conf_lc {
267 nvidia,pins = "lc", "ls";
268 nvidia,pull = <TEGRA_PIN_PULL_UP>;
269 };
270 conf_lcsn {
271 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
272 "lm0", "lm1", "lpp", "lpw0", "lpw1",
273 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
274 "lvp0", "lvp1", "sdb";
275 nvidia,tristate = <TEGRA_PIN_ENABLE>;
276 };
277 conf_ld17_0 {
278 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
279 "ld23_22";
280 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Allen Martin0398dcb2013-01-16 13:12:24 +0000281 };
282 };
283 };
284
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300285 i2s@70002800 {
286 status = "okay";
287 };
288
Stephen Warren24bfee62012-05-21 10:04:37 +0000289 serial@70006000 {
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300290 status = "okay";
291 };
292
293 serial@70006200 {
294 status = "okay";
295 };
296
297 pwm: pwm@7000a000 {
298 status = "okay";
Stephen Warren24bfee62012-05-21 10:04:37 +0000299 };
300
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300301 lvds_ddc: i2c@7000c000 {
302 status = "okay";
303 clock-frequency = <400000>;
304
305 alc5632: alc5632@1e {
306 compatible = "realtek,alc5632";
307 reg = <0x1e>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 };
311 };
312
313 hdmi_ddc: i2c@7000c400 {
314 status = "okay";
315 clock-frequency = <100000>;
316 };
317
Thierry Reding57595aa2023-07-10 11:22:18 +0200318 i2c@7000c500 {
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300319 compatible = "nvidia,nvec";
Thierry Reding57595aa2023-07-10 11:22:18 +0200320
321 /delete-property/ #address-cells;
322 /delete-property/ #size-cells;
323 /delete-property/ dmas;
324 /delete-property/ dma-names;
325
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300326 clock-frequency = <80000>;
327 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
328 slave-addr = <138>;
Thierry Reding57595aa2023-07-10 11:22:18 +0200329
330 status = "okay";
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300331 };
332
333 i2c@7000d000 {
334 status = "okay";
335 clock-frequency = <400000>;
336
337 pmic: tps6586x@34 {
338 compatible = "ti,tps6586x";
339 reg = <0x34>;
340 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
341
342 #gpio-cells = <2>;
343 gpio-controller;
344
345 sys-supply = <&p5valw_reg>;
346 vin-sm0-supply = <&sys_reg>;
347 vin-sm1-supply = <&sys_reg>;
348 vin-sm2-supply = <&sys_reg>;
349 vinldo01-supply = <&sm2_reg>;
350 vinldo23-supply = <&sm2_reg>;
351 vinldo4-supply = <&sm2_reg>;
352 vinldo678-supply = <&sm2_reg>;
353 vinldo9-supply = <&sm2_reg>;
354
355 regulators {
356 sys_reg: sys {
357 regulator-name = "vdd_sys";
358 regulator-always-on;
359 };
360
361 sm0 {
362 regulator-name = "+1.2vs_sm0,vdd_core";
363 regulator-min-microvolt = <1200000>;
364 regulator-max-microvolt = <1200000>;
365 regulator-always-on;
366 };
367
368 sm1 {
369 regulator-name = "+1.0vs_sm1,vdd_cpu";
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
372 regulator-always-on;
373 };
374
375 sm2_reg: sm2 {
376 regulator-name = "+3.7vs_sm2,vin_ldo*";
377 regulator-min-microvolt = <3700000>;
378 regulator-max-microvolt = <3700000>;
379 regulator-always-on;
380 };
381
382 /* LDO0 is not connected to anything */
383
384 ldo1 {
385 regulator-name = "+1.1vs_ldo1,avdd_pll*";
386 regulator-min-microvolt = <1100000>;
387 regulator-max-microvolt = <1100000>;
388 regulator-always-on;
389 };
390
391 ldo2 {
392 regulator-name = "+1.2vs_ldo2,vdd_rtc";
393 regulator-min-microvolt = <1200000>;
394 regulator-max-microvolt = <1200000>;
395 };
396
397 ldo3 {
398 regulator-name = "+3.3vs_ldo3,avdd_usb*";
399 regulator-min-microvolt = <3300000>;
400 regulator-max-microvolt = <3300000>;
401 regulator-always-on;
402 };
403
404 ldo4 {
405 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
406 regulator-min-microvolt = <1800000>;
407 regulator-max-microvolt = <1800000>;
408 regulator-always-on;
409 };
410
411 ldo5 {
412 regulator-name = "+2.85vs_ldo5,vcore_mmc";
413 regulator-min-microvolt = <2850000>;
414 regulator-max-microvolt = <2850000>;
415 regulator-always-on;
416 };
417
418 ldo6 {
419 /*
420 * Research indicates this should be
421 * 1.8v; other boards that use this
422 * rail for the same purpose need it
423 * set to 1.8v. The schematic signal
424 * name is incorrect; perhaps copied
425 * from an incorrect NVIDIA reference.
426 */
427 regulator-name = "+2.85vs_ldo6,avdd_vdac";
428 regulator-min-microvolt = <1800000>;
429 regulator-max-microvolt = <1800000>;
430 };
431
432 hdmi_vdd_reg: ldo7 {
433 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
434 regulator-min-microvolt = <3300000>;
435 regulator-max-microvolt = <3300000>;
436 };
437
438 hdmi_pll_reg: ldo8 {
439 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
440 regulator-min-microvolt = <1800000>;
441 regulator-max-microvolt = <1800000>;
442 };
443
444 ldo9 {
445 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
446 regulator-min-microvolt = <2850000>;
447 regulator-max-microvolt = <2850000>;
448 regulator-always-on;
449 };
450
451 ldo_rtc {
452 regulator-name = "+3.3vs_rtc";
453 regulator-min-microvolt = <3300000>;
454 regulator-max-microvolt = <3300000>;
455 regulator-always-on;
456 };
457 };
458 };
459
460 adt7461@4c {
461 compatible = "adi,adt7461";
462 reg = <0x4c>;
463 };
464 };
465
466 pmc@7000e400 {
467 nvidia,invert-interrupt;
468 nvidia,suspend-mode = <1>;
469 nvidia,cpu-pwr-good-time = <2000>;
470 nvidia,cpu-pwr-off-time = <0>;
471 nvidia,core-pwr-good-time = <3845 3845>;
472 nvidia,core-pwr-off-time = <0>;
473 nvidia,sys-clock-req-active-high;
474 };
475
476 usb@c5000000 {
477 status = "okay";
478 };
479
480 usb-phy@c5000000 {
481 status = "okay";
482 };
483
484 usb@c5004000 {
485 status = "okay";
486 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
487 GPIO_ACTIVE_LOW>;
488 };
489
490 usb-phy@c5004000 {
491 status = "okay";
492 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
493 GPIO_ACTIVE_LOW>;
494 };
495
Simon Glasse31a2a52016-01-30 16:37:52 -0700496 usb@c5008000 {
497 status = "okay";
Stephen Warren24bfee62012-05-21 10:04:37 +0000498 };
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000499
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300500 usb-phy@c5008000 {
501 status = "okay";
502 };
503
Tom Warrened955272013-02-21 12:31:29 +0000504 sdhci@c8000000 {
505 status = "okay";
Simon Glass3112fd52015-01-05 20:05:41 -0700506 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
507 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
508 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Tom Warrened955272013-02-21 12:31:29 +0000509 bus-width = <4>;
510 };
511
512 sdhci@c8000600 {
513 status = "okay";
514 bus-width = <8>;
Tom Warren1c77f022016-09-13 10:45:42 -0600515 non-removable;
Tom Warrened955272013-02-21 12:31:29 +0000516 };
517
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300518 backlight: backlight {
519 compatible = "pwm-backlight";
520
521 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
522 power-supply = <&vdd_bl_reg>;
523 pwms = <&pwm 0 5000000>;
524
525 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
526 default-brightness-level = <10>;
527
528 backlight-boot-off;
529 };
530
Simon Glasse31a2a52016-01-30 16:37:52 -0700531 clocks {
532 compatible = "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <0>;
535
536 clk32k_in: clock@0 {
537 compatible = "fixed-clock";
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300538 reg = <0>;
Simon Glasse31a2a52016-01-30 16:37:52 -0700539 #clock-cells = <0>;
540 clock-frequency = <32768>;
541 };
542 };
543
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300544 gpio-keys {
545 compatible = "gpio-keys";
546
547 power {
548 label = "Power";
549 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
550 linux,code = <KEY_POWER>;
551 wakeup-source;
552 };
Simon Glassd8af3c92016-01-30 16:38:01 -0700553 };
554
Misha Komarovskiy2ed0fc12016-12-11 22:28:12 +0300555 gpio-leds {
556 compatible = "gpio-leds";
557
558 wifi {
559 label = "wifi-led";
560 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
561 linux,default-trigger = "rfkill0";
562 };
563 };
564
565 panel: panel {
566 compatible = "samsung,ltn101nt05", "simple-panel";
567
568 ddc-i2c-bus = <&lvds_ddc>;
569 power-supply = <&vdd_pnl_reg>;
570 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
571
572 backlight = <&backlight>;
573 };
574
575 regulators {
576 compatible = "simple-bus";
577 #address-cells = <1>;
578 #size-cells = <0>;
579
580 p5valw_reg: regulator@0 {
581 compatible = "regulator-fixed";
582 reg = <0>;
583 regulator-name = "+5valw";
584 regulator-min-microvolt = <5000000>;
585 regulator-max-microvolt = <5000000>;
586 regulator-always-on;
587 };
588
589 vdd_pnl_reg: regulator@1 {
590 compatible = "regulator-fixed";
591 reg = <1>;
592 regulator-name = "+3VS,vdd_pnl";
593 regulator-min-microvolt = <3300000>;
594 regulator-max-microvolt = <3300000>;
595 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
596 enable-active-high;
597 };
598
599 vdd_bl_reg: regulator@2 {
600 compatible = "regulator-fixed";
601 reg = <2>;
602 regulator-name = "vdd_bl";
603 regulator-min-microvolt = <2800000>;
604 regulator-max-microvolt = <2800000>;
605 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
606 enable-active-high;
607 };
608 };
609
610 sound {
611 compatible = "nvidia,tegra-audio-alc5632-paz00",
612 "nvidia,tegra-audio-alc5632";
613
614 nvidia,model = "Compal PAZ00";
615
616 nvidia,audio-routing =
617 "Int Spk", "SPKOUT",
618 "Int Spk", "SPKOUTN",
619 "Headset Mic", "MICBIAS1",
620 "MIC1", "Headset Mic",
621 "Headset Stereophone", "HPR",
622 "Headset Stereophone", "HPL",
623 "DMICDAT", "Digital Mic";
624
625 nvidia,audio-codec = <&alc5632>;
626 nvidia,i2s-controller = <&tegra_i2s1>;
627 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
628 GPIO_ACTIVE_HIGH>;
629
630 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
631 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
632 <&tegra_car TEGRA20_CLK_CDEV1>;
633 clock-names = "pll_a", "pll_a_out0", "mclk";
Marc Dietrichb81dfe12012-11-25 11:26:12 +0000634 };
Stephen Warren24bfee62012-05-21 10:04:37 +0000635};