| Simon Glass | c052918 | 2020-09-22 12:44:47 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2015 Google Inc. |
| 4 | * Copyright (C) 2018 Intel Corporation. |
| 5 | */ |
| 6 | |
| 7 | #include <intelblocks/pcr.h> |
| 8 | |
| 9 | /* |
| 10 | * Calculate PCR register base at specified PID |
| 11 | * Arg0 - PCR Port ID |
| 12 | */ |
| 13 | Method (PCRB, 1, NotSerialized) |
| 14 | { |
| 15 | Return (Add (IOMAP_P2SB_BAR, |
| 16 | ShiftLeft (Arg0, PCR_PORTID_SHIFT))) |
| 17 | } |
| 18 | |
| 19 | /* |
| 20 | * Read a PCR register at specified PID and offset |
| 21 | * Arg0 - PCR Port ID |
| 22 | * Arg1 - Register Offset |
| 23 | */ |
| 24 | Method (PCRR, 2, Serialized) |
| 25 | { |
| 26 | OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) |
| 27 | Field (PCRD, DWordAcc, NoLock, Preserve) |
| 28 | { |
| 29 | DATA, 32 |
| 30 | } |
| 31 | Return (DATA) |
| 32 | } |
| 33 | |
| 34 | /* |
| 35 | * AND a value with PCR register at specified PID and offset |
| 36 | * Arg0 - PCR Port ID |
| 37 | * Arg1 - Register Offset |
| 38 | * Arg2 - Value to AND |
| 39 | */ |
| 40 | Method (PCRA, 3, Serialized) |
| 41 | { |
| 42 | OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) |
| 43 | Field (PCRD, DWordAcc, NoLock, Preserve) |
| 44 | { |
| 45 | DATA, 32 |
| 46 | } |
| 47 | And (DATA, Arg2, DATA) |
| 48 | |
| 49 | /* |
| 50 | * After every write one needs to read an innocuous register |
| 51 | * to ensure the writes are completed for certain ports. This is done |
| 52 | * for all ports so that the callers don't need the per-port knowledge |
| 53 | * for each transaction. |
| 54 | */ |
| 55 | PCRR (Arg0, Arg1) |
| 56 | } |
| 57 | |
| 58 | /* |
| 59 | * OR a value with PCR register at specified PID and offset |
| 60 | * Arg0 - PCR Port ID |
| 61 | * Arg1 - Register Offset |
| 62 | * Arg2 - Value to OR |
| 63 | */ |
| 64 | Method (PCRO, 3, Serialized) |
| 65 | { |
| 66 | OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) |
| 67 | Field (PCRD, DWordAcc, NoLock, Preserve) |
| 68 | { |
| 69 | DATA, 32 |
| 70 | } |
| 71 | Or (DATA, Arg2, DATA) |
| 72 | |
| 73 | /* |
| 74 | * After every write one needs to read an innocuous register |
| 75 | * to ensure the writes are completed for certain ports. This is done |
| 76 | * for all ports so that the callers don't need the per-port knowledge |
| 77 | * for each transaction. |
| 78 | */ |
| 79 | PCRR (Arg0, Arg1) |
| 80 | } |