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trem0053e3c2013-09-10 22:08:39 +02001/*
2 *
3 * Configuration settings for the Armadeus Project motherboard APF27
4 *
5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
trem0053e3c2013-09-10 22:08:39 +020013#define CONFIG_ENV_VERSION 10
trem0053e3c2013-09-10 22:08:39 +020014#define CONFIG_BOARD_NAME apf27
15
16/*
17 * SoC configurations
18 */
Masahiro Yamada4fb5d072014-11-06 14:59:36 +090019#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
trem0053e3c2013-09-10 22:08:39 +020020#define CONFIG_MACH_TYPE 1698 /* APF27 */
trem0053e3c2013-09-10 22:08:39 +020021
22/*
23 * Enable the call to miscellaneous platform dependent initialization.
24 */
trem0053e3c2013-09-10 22:08:39 +020025
26/*
trem0053e3c2013-09-10 22:08:39 +020027 * SPL
28 */
trem0053e3c2013-09-10 22:08:39 +020029#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
trem0053e3c2013-09-10 22:08:39 +020030#define CONFIG_SPL_MAX_SIZE 2048
31#define CONFIG_SPL_TEXT_BASE 0xA0000000
32
33/* NAND boot config */
trem0053e3c2013-09-10 22:08:39 +020034#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
36#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
37#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
38
39/*
40 * BOOTP options
41 */
42#define CONFIG_BOOTP_SUBNETMASK
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45#define CONFIG_BOOTP_BOOTPATH
46#define CONFIG_BOOTP_BOOTFILESIZE
47#define CONFIG_BOOTP_DNS
48#define CONFIG_BOOTP_DNS2
49
50#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
51#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
52
53/*
trem0053e3c2013-09-10 22:08:39 +020054 * Memory configurations
55 */
56#define CONFIG_NR_DRAM_POPULATED 1
57#define CONFIG_NR_DRAM_BANKS 2
58
59#define ACFG_SDRAM_MBYTE_SYZE 64
60
61#define PHYS_SDRAM_1 0xA0000000
62#define PHYS_SDRAM_2 0xB0000000
63#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
64#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
65#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
66#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
67
68#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
69 + PHYS_SDRAM_1_SIZE - 0x0100000)
70
71#define CONFIG_SYS_TEXT_BASE 0xA0000800
72
73/*
74 * FLASH organization
75 */
76#define ACFG_MONITOR_OFFSET 0x00000000
77#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
trem0053e3c2013-09-10 22:08:39 +020078#define CONFIG_ENV_OVERWRITE
79#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
80#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
81#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
82#define CONFIG_ENV_OFFSET_REDUND \
83 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
84#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
85#define CONFIG_FIRMWARE_OFFSET 0x00200000
86#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
87#define CONFIG_KERNEL_OFFSET 0x00300000
88#define CONFIG_ROOTFS_OFFSET 0x00800000
89
trem0053e3c2013-09-10 22:08:39 +020090/*
91 * U-Boot general configurations
92 */
93#define CONFIG_SYS_LONGHELP
trem0053e3c2013-09-10 22:08:39 +020094#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
trem0053e3c2013-09-10 22:08:39 +020095#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
96 /* Boot argument buffer size */
97#define CONFIG_AUTO_COMPLETE
98#define CONFIG_CMDLINE_EDITING
trem0053e3c2013-09-10 22:08:39 +020099#define CONFIG_ENV_VARS_UBOOT_CONFIG
100#define CONFIG_PREBOOT "run check_flash check_env;"
101
trem0053e3c2013-09-10 22:08:39 +0200102/*
103 * Boot Linux
104 */
105#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
106#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
107#define CONFIG_INITRD_TAG /* send initrd params */
108
trem0053e3c2013-09-10 22:08:39 +0200109#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
trem0053e3c2013-09-10 22:08:39 +0200110
111#define ACFG_CONSOLE_DEV ttySMX0
112#define CONFIG_BOOTCOMMAND "run ubifsboot"
113#define CONFIG_SYS_AUTOLOAD "no"
114/*
115 * Default load address for user programs and kernel
116 */
117#define CONFIG_LOADADDR 0xA0000000
118#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
119
120/*
121 * Extra Environments
122 */
123#define CONFIG_EXTRA_ENV_SETTINGS \
124 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
125 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
Tom Rini5ad8e112017-10-22 17:55:07 -0400126 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
trem0053e3c2013-09-10 22:08:39 +0200127 "partition=nand0,6\0" \
128 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
129 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
130 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
131 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
132 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
133 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
134 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
135 "kernel_addr_r=A0000000\0" \
136 "check_env=if test -n ${flash_env_version}; " \
137 "then env default env_version; " \
138 "else env set flash_env_version ${env_version}; env save; "\
139 "fi; " \
140 "if itest ${flash_env_version} < ${env_version}; then " \
141 "echo \"*** Warning - Environment version" \
142 " change suggests: run flash_reset_env; reset\"; "\
143 "env default flash_reset_env; "\
144 "fi; \0" \
145 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
146 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
147 "echo Flash environment variables erased!\0" \
148 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
149 "-u-boot-with-spl.bin\0" \
150 "flash_uboot=nand unlock ${u-boot_addr} ;" \
151 "nand erase.part u-boot;" \
152 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
153 "then nand lock; nand unlock ${env_addr};" \
154 "echo Flashing of uboot succeed;" \
155 "else echo Flashing of uboot failed;" \
156 "fi; \0" \
157 "update_uboot=run download_uboot flash_uboot\0" \
158 "download_env=tftpboot ${loadaddr} ${board_name}" \
159 "-u-boot-env.txt\0" \
160 "flash_env=env import -t ${loadaddr}; env save; \0" \
161 "update_env=run download_env flash_env\0" \
162 "update_all=run update_env update_uboot\0" \
163 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
164
165/*
166 * Serial Driver
167 */
168#define CONFIG_MXC_UART
169#define CONFIG_CONS_INDEX 1
trem0053e3c2013-09-10 22:08:39 +0200170#define CONFIG_MXC_UART_BASE UART1_BASE
171
172/*
173 * GPIO
174 */
175#define CONFIG_MXC_GPIO
176
177/*
178 * NOR
179 */
180
181/*
182 * NAND
183 */
trem0053e3c2013-09-10 22:08:39 +0200184
185#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
186#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
187#define CONFIG_SYS_MAX_NAND_DEVICE 1
188
189#define CONFIG_MXC_NAND_HWECC
190#define CONFIG_SYS_NAND_LARGEPAGE
trem0053e3c2013-09-10 22:08:39 +0200191#define CONFIG_SYS_NAND_PAGE_SIZE 2048
192#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
193#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
194 CONFIG_SYS_NAND_PAGE_SIZE
195#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
196#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
197#define NAND_MAX_CHIPS 1
198
199#define CONFIG_FLASH_SHOW_PROGRESS 45
200#define CONFIG_SYS_NAND_QUIET 1
201
202/*
203 * Partitions & Filsystems
204 */
205#define CONFIG_MTD_DEVICE
206#define CONFIG_MTD_PARTITIONS
trem0053e3c2013-09-10 22:08:39 +0200207
208/*
trem0053e3c2013-09-10 22:08:39 +0200209 * Ethernet (on SOC imx FEC)
210 */
211#define CONFIG_FEC_MXC
212#define CONFIG_FEC_MXC_PHYADDR 0x1f
213#define CONFIG_MII /* MII PHY management */
214
215/*
trem97852892013-09-10 22:08:40 +0200216 * FPGA
217 */
218#ifndef CONFIG_SPL_BUILD
219#define CONFIG_FPGA
220#endif
221#define CONFIG_FPGA_COUNT 1
222#define CONFIG_FPGA_XILINX
223#define CONFIG_FPGA_SPARTAN3
224#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
225#define CONFIG_SYS_FPGA_PROG_FEEDBACK
226#define CONFIG_SYS_FPGA_CHECK_CTRLC
227#define CONFIG_SYS_FPGA_CHECK_ERROR
228
229/*
trem0053e3c2013-09-10 22:08:39 +0200230 * Fuses - IIM
231 */
232#ifdef CONFIG_CMD_IMX_FUSE
233#define IIM_MAC_BANK 0
234#define IIM_MAC_ROW 5
235#define IIM0_SCC_KEY 11
236#define IIM1_SUID 1
237#endif
238
239/*
240 * I2C
241 */
242
243#ifdef CONFIG_CMD_I2C
trem03997412013-09-21 18:13:36 +0200244#define CONFIG_SYS_I2C
245#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200246#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
247#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
trem03997412013-09-21 18:13:36 +0200248#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
249#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
250#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
251#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
trem0053e3c2013-09-10 22:08:39 +0200252#define CONFIG_SYS_I2C_NOPROBES { }
253
254#ifdef CONFIG_CMD_EEPROM
255# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
256# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
257#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
258#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
259#endif /* CONFIG_CMD_EEPROM */
260#endif /* CONFIG_CMD_I2C */
261
262/*
263 * SD/MMC
264 */
265#ifdef CONFIG_CMD_MMC
trem0053e3c2013-09-10 22:08:39 +0200266#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
267#endif
268
269/*
270 * RTC
271 */
272#ifdef CONFIG_CMD_DATE
273#define CONFIG_RTC_DS1374
274#define CONFIG_SYS_RTC_BUS_NUM 0
275#endif /* CONFIG_CMD_DATE */
276
277/*
trem0053e3c2013-09-10 22:08:39 +0200278 * PLL
279 *
280 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
281 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
282 */
283#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
284
285#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
286/* micron 64MB */
287#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
288#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
289#endif
290
291#if (ACFG_SDRAM_MBYTE_SYZE == 128)
292/* micron 128MB */
293#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
294#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
295#endif
296
297#if (ACFG_SDRAM_MBYTE_SYZE == 256)
298/* micron 256MB */
299#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
300#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
301#endif
302
303#endif /* __CONFIG_H */