| Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * U-Boot additions |
| 4 | * |
| 5 | * Copyright (C) 2024 Intel Corporation <www.intel.com> |
| 6 | */ |
| 7 | |
| 8 | #include "socfpga_agilex5-u-boot.dtsi" |
| 9 | |
| 10 | /{ |
| 11 | aliases { |
| 12 | spi0 = &qspi; |
| 13 | freeze_br0 = &freeze_controller; |
| 14 | }; |
| 15 | |
| 16 | soc { |
| 17 | freeze_controller: freeze_controller@0x20000450 { |
| 18 | compatible = "altr,freeze-bridge-controller"; |
| 19 | reg = <0x20000450 0x00000010>; |
| 20 | status = "disabled"; |
| 21 | }; |
| 22 | }; |
| 23 | |
| 24 | memory { |
| 25 | /* 8GB */ |
| 26 | reg = <0 0x80000000 0 0x80000000>, |
| 27 | <8 0x80000000 1 0x80000000>; |
| 28 | }; |
| 29 | |
| 30 | chosen { |
| 31 | stdout-path = "serial0:115200n8"; |
| 32 | u-boot,spl-boot-order = &mmc,&flash0,"/memory"; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | &flash0 { |
| 37 | compatible = "jedec,spi-nor"; |
| 38 | spi-tx-bus-width = <4>; |
| 39 | spi-rx-bus-width = <4>; |
| 40 | bootph-all; |
| 41 | /delete-property/ cdns,read-delay; |
| 42 | }; |
| 43 | |
| 44 | &i3c0 { |
| 45 | bootph-all; |
| 46 | }; |
| 47 | |
| 48 | &i3c1 { |
| 49 | bootph-all; |
| 50 | }; |
| 51 | |
| 52 | &mmc { |
| 53 | status = "okay"; |
| 54 | bus-width = <4>; |
| 55 | sd-uhs-sdr50; |
| 56 | cap-mmc-highspeed; |
| 57 | bootph-all; |
| 58 | }; |
| 59 | |
| 60 | &combophy0 { |
| 61 | status = "okay"; |
| 62 | bootph-all; |
| 63 | cdns,phy-use-ext-lpbk-dqs = <1>; |
| 64 | cdns,phy-use-lpbk-dqs = <1>; |
| 65 | cdns,phy-use-phony-dqs = <1>; |
| 66 | cdns,phy-use-phony-dqs-cmd = <1>; |
| 67 | cdns,phy-io-mask-always-on = <0>; |
| 68 | cdns,phy-io-mask-end = <5>; |
| 69 | cdns,phy-io-mask-start = <0>; |
| 70 | cdns,phy-data-select-oe-end = <1>; |
| 71 | cdns,phy-sync-method = <1>; |
| 72 | cdns,phy-sw-half-cycle-shift = <0>; |
| 73 | cdns,phy-rd-del-sel = <52>; |
| 74 | cdns,phy-underrun-suppress = <1>; |
| 75 | cdns,phy-gate-cfg-always-on = <1>; |
| 76 | cdns,phy-param-dll-bypass-mode = <1>; |
| 77 | cdns,phy-param-phase-detect-sel = <2>; |
| 78 | cdns,phy-param-dll-start-point = <254>; |
| 79 | cdns,phy-read-dqs-cmd-delay = <0>; |
| 80 | cdns,phy-clk-wrdqs-delay = <0>; |
| 81 | cdns,phy-clk-wr-delay = <0>; |
| 82 | cdns,phy-read-dqs-delay = <0>; |
| 83 | cdns,phy-phony-dqs-timing = <0>; |
| 84 | cdns,hrs09-rddata-en = <1>; |
| 85 | cdns,hrs09-rdcmd-en = <1>; |
| 86 | cdns,hrs09-extended-wr-mode = <1>; |
| 87 | cdns,hrs09-extended-rd-mode = <1>; |
| 88 | cdns,hrs10-hcsdclkadj = <3>; |
| 89 | cdns,hrs16-wrdata1-sdclk-dly = <0>; |
| 90 | cdns,hrs16-wrdata0-sdclk-dly = <0>; |
| 91 | cdns,hrs16-wrcmd1-sdclk-dly = <0>; |
| 92 | cdns,hrs16-wrcmd0-sdclk-dly = <0>; |
| 93 | cdns,hrs16-wrdata1-dly = <0>; |
| 94 | cdns,hrs16-wrdata0-dly = <0>; |
| 95 | cdns,hrs16-wrcmd1-dly = <0>; |
| 96 | cdns,hrs16-wrcmd0-dly = <0>; |
| 97 | cdns,hrs07-rw-compensate = <10>; |
| 98 | cdns,hrs07-idelay-val = <0>; |
| 99 | }; |
| 100 | |
| 101 | &qspi { |
| 102 | status = "okay"; |
| 103 | }; |
| 104 | |
| 105 | &timer0 { |
| 106 | bootph-all; |
| 107 | }; |
| 108 | |
| 109 | &timer1 { |
| 110 | bootph-all; |
| 111 | }; |
| 112 | |
| 113 | &timer2 { |
| 114 | bootph-all; |
| 115 | }; |
| 116 | |
| 117 | &timer3 { |
| 118 | bootph-all; |
| 119 | }; |
| 120 | |
| 121 | &watchdog0 { |
| 122 | bootph-all; |
| 123 | }; |
| 124 | |