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git01.mediatek.com / filogic / uboot / 514628ce926c329c2e5736b7ed0ae590e1614da1 / . / arch / arm / dts / imx8mm-phyboard-polis-rdk.dts
blob: 03e7679217b24d9f09381a437fffdfabf8d167a9 [file] [log] [blame]
Cem Tenruhdbc57052023-07-14 10:23:26 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12#include "imx8mm-phycore-som.dtsi"
13
14/ {
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
18
19 chosen {
20 stdout-path = &uart3;
21 };
22
23 bt_osc_32k: bt-lp-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
26 clock-output-names = "bt_osc_32k";
27 #clock-cells = <0>;
28 };
29
30 can_osc_40m: can-clock {
31 compatible = "fixed-clock";
32 clock-frequency = <40000000>;
33 clock-output-names = "can_osc_40m";
34 #clock-cells = <0>;
35 };
36
37 fan {
38 compatible = "gpio-fan";
39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
40 gpio-fan,speed-map = <0 0
41 13000 1>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_fan>;
44 #cooling-cells = <2>;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_leds>;
51
52 led-0 {
53 color = <LED_COLOR_ID_RED>;
54 function = LED_FUNCTION_DISK;
55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger = "mmc2";
57 };
58
59 led-1 {
60 color = <LED_COLOR_ID_BLUE>;
61 function = LED_FUNCTION_DISK;
62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "mmc1";
64 };
65
66 led-2 {
67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTION_CPU;
69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger = "heartbeat";
71 };
72 };
73
74 usdhc1_pwrseq: pwr-seq {
75 compatible = "mmc-pwrseq-simple";
76 post-power-on-delay-ms = <100>;
77 power-off-delay-us = <60>;
78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
79 };
80
81 reg_can_en: regulator-can-en {
82 compatible = "regulator-fixed";
83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_can_en>;
86 regulator-max-microvolt = <3300000>;
87 regulator-min-microvolt = <3300000>;
88 regulator-name = "CAN_EN";
89 startup-delay-us = <20>;
90 };
91
92 reg_usb_otg1_vbus: regulator-usb-otg1 {
93 compatible = "regulator-fixed";
94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
95 enable-active-high;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
98 regulator-name = "usb_otg1_vbus";
99 regulator-max-microvolt = <5000000>;
100 regulator-min-microvolt = <5000000>;
101 };
102
103 reg_usdhc2_vmmc: regulator-usdhc2 {
104 compatible = "regulator-fixed";
105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
106 enable-active-high;
107 off-on-delay-us = <20000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
110 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <3300000>;
112 regulator-name = "VSD_3V3";
113 };
114
115 reg_vcc_3v3: regulator-vcc-3v3 {
116 compatible = "regulator-fixed";
117 regulator-max-microvolt = <3300000>;
118 regulator-min-microvolt = <3300000>;
119 regulator-name = "VCC_3V3";
120 };
121};
122
123/* SPI - CAN MCP251XFD */
124&ecspi1 {
125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_ecspi1>;
128 status = "okay";
129
130 can0: can@0 {
131 compatible = "microchip,mcp251xfd";
132 clocks = <&can_osc_40m>;
133 interrupt-parent = <&gpio1>;
134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_can_int>;
137 reg = <0>;
138 spi-max-frequency = <20000000>;
139 xceiver-supply = <&reg_can_en>;
140 };
141};
142
143&gpio1 {
144 gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
145 "", "", "", "RESET_ETHPHY",
146 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
147 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
148};
149
150&gpio2 {
151 gpio-line-names = "", "", "", "",
152 "", "", "BT_REG_ON", "WL_REG_ON",
153 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
154 "X_SD2_CD_B", "", "", "",
155 "", "", "", "SD2_RESET_B";
156};
157
158&gpio4 {
159 gpio-line-names = "", "", "", "",
160 "", "", "", "",
161 "FAN", "miniPCIe_nPERST", "", "",
162 "COEX1", "COEX2";
163};
164
165&gpio5 {
166 gpio-line-names = "", "", "", "",
167 "", "", "", "",
168 "", "ECSPI1_SS0";
169};
170
171&i2c4 {
172 clock-frequency = <400000>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c4>;
175};
176
177/* PCIe */
178&pcie0 {
179 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
180 <&clk IMX8MM_CLK_PCIE1_CTRL>;
181 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
182 <&clk IMX8MM_SYS_PLL2_250M>;
183 assigned-clock-rates = <10000000>, <250000000>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_pcie>;
186 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
187 status = "okay";
188};
189
190&pcie_phy {
191 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
192 fsl,clkreq-unsupported;
193 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
194 fsl,tx-deemph-gen1 = <0x2d>;
195 fsl,tx-deemph-gen2 = <0xf>;
196 status = "okay";
197};
198
199&rv3028 {
200 trickle-resistor-ohms = <3000>;
201};
202
203&snvs_pwrkey {
204 status = "okay";
205};
206
207/* UART - RS232/RS485 */
208&uart1 {
209 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
210 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_uart1>;
213 uart-has-rtscts;
214 status = "okay";
215};
216
217/* UART - Sterling-LWB Bluetooth */
218&uart2 {
219 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
220 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
221 fsl,dte-mode;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_uart2_bt>;
224 uart-has-rtscts;
225 status = "okay";
226
227 bluetooth {
228 compatible = "brcm,bcm43438-bt";
229 clocks = <&bt_osc_32k>;
230 clock-names = "lpo";
231 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
232 interrupt-names = "host-wakeup";
233 interrupt-parent = <&gpio2>;
234 interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
235 max-speed = <2000000>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_bt>;
238 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
239 vddio-supply = <&reg_vcc_3v3>;
240 };
241};
242
243/* UART - console */
244&uart3 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart3>;
247 status = "okay";
248};
249
250/* USB */
251&usbotg1 {
252 adp-disable;
253 dr_mode = "otg";
254 over-current-active-low;
255 samsung,picophy-pre-emp-curr-control = <3>;
256 samsung,picophy-dc-vol-level-adjust = <7>;
257 srp-disable;
258 vbus-supply = <&reg_usb_otg1_vbus>;
259 status = "okay";
260};
261
262&usbotg2 {
263 disable-over-current;
264 dr_mode = "host";
265 samsung,picophy-pre-emp-curr-control = <3>;
266 samsung,picophy-dc-vol-level-adjust = <7>;
267 status = "okay";
268};
269
270/* SDIO - Sterling-LWB Wifi */
271&usdhc1 {
272 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
273 assigned-clock-rates = <200000000>;
274 bus-width = <4>;
275 mmc-pwrseq = <&usdhc1_pwrseq>;
276 non-removable;
277 no-1-8-v;
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "okay";
283
284 brcmf: wifi@1 {
285 compatible = "brcm,bcm4329-fmac";
286 reg = <1>;
287 };
288};
289
290/* SD-Card */
291&usdhc2 {
292 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
293 assigned-clock-rates = <200000000>;
294 bus-width = <4>;
295 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
296 disable-wp;
297 pinctrl-names = "default", "state_100mhz", "state_200mhz";
298 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
299 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
300 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
301 vmmc-supply = <&reg_usdhc2_vmmc>;
302 vqmmc-supply = <&reg_nvcc_sd2>;
303 status = "okay";
304};
305
306&iomuxc {
307 pinctrl_bt: btgrp {
308 fsl,pins = <
309 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
310 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
311 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
312 >;
313 };
314
315 pinctrl_can_en: can-engrp {
316 fsl,pins = <
317 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
318 >;
319 };
320
321 pinctrl_can_int: can-intgrp {
322 fsl,pins = <
323 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
324 >;
325 };
326
327 pinctrl_ecspi1: ecspi1grp {
328 fsl,pins = <
329 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
330 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
331 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
332 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
333 >;
334 };
335
336 pinctrl_fan: fan0grp {
337 fsl,pins = <
338 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
339 >;
340 };
341
342 pinctrl_i2c4: i2c4grp {
343 fsl,pins = <
344 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
345 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
346 >;
347 };
348
349 pinctrl_leds: leds1grp {
350 fsl,pins = <
351 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
352 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
353 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
354 >;
355 };
356
357 pinctrl_pcie: pciegrp {
358 fsl,pins = <
359 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
360 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
361 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
362 >;
363 };
364
365 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
366 fsl,pins = <
367 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
368 >;
369 };
370
371 pinctrl_uart1: uart1grp {
372 fsl,pins = <
373 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
374 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
375 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
376 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
377 >;
378 };
379
380 pinctrl_uart2_bt: uart2btgrp {
381 fsl,pins = <
382 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
383 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
384 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
385 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
386 >;
387 };
388
389 pinctrl_uart3: uart3grp {
390 fsl,pins = <
391 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
392 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
393 >;
394 };
395
396 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
397 fsl,pins = <
398 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
399 >;
400 };
401
402 pinctrl_usdhc1: usdhc1grp {
403 fsl,pins = <
404 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
405 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
406 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
407 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
408 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
409 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
410 >;
411 };
412
413 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
414 fsl,pins = <
415 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
416 >;
417 };
418
419 pinctrl_usdhc2: usdhc2grp {
420 fsl,pins = <
421 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
422 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
423 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
424 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
425 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
426 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
427 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
428 >;
429 };
430
431 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
432 fsl,pins = <
433 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
434 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
435 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
436 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
437 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
438 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
439 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
440 >;
441 };
442
443 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
444 fsl,pins = <
445 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
446 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
447 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
448 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
449 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
450 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
451 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
452 >;
453 };
454
455 pinctrl_wlan: wlangrp {
456 fsl,pins = <
457 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
458 >;
459 };
460};